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-rw-r--r--src/test/scala/chiselTests/Risc.scala4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/test/scala/chiselTests/Risc.scala b/src/test/scala/chiselTests/Risc.scala
index c110d37e..156e5df2 100644
--- a/src/test/scala/chiselTests/Risc.scala
+++ b/src/test/scala/chiselTests/Risc.scala
@@ -8,7 +8,7 @@ import chisel3.util._
class Risc extends Module {
val io = IO(new Bundle {
val isWr = Input(Bool())
- val wrAddr = Input(UInt(8))
+ val wrAddr = Input(UInt.width(8))
val wrData = Input(Bits(32))
val boot = Input(Bool())
val valid = Output(Bool())
@@ -38,7 +38,7 @@ class Risc extends Module {
when (io.isWr) {
code(io.wrAddr) := io.wrData
} .elsewhen (io.boot) {
- pc := UInt(0)
+ pc := UInt.Lit(0)
} .otherwise {
switch(op) {
is(add_op) { rc := ra +% rb }