Distinguish between ?Int.Lit and ?Int.width

5 files changed, 47 insertions, 25 deletions

diff --git a/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala b/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala
index 666d8283..a80dfec8 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala
@@ -241,7 +241,7 @@ trait VecLike[T <: Data] extends collection.IndexedSeq[T] with HasId {
   /** Helper function that appends an index (literal value) to each element,
     * useful for hardware generators which output an index.
     */
-  private def indexWhereHelper(p: T => Bool) = this map p zip (0 until length).map(i => UInt(i))
+  private def indexWhereHelper(p: T => Bool) = this map p zip (0 until length).map(i => UInt.Lit(i))
 
   /** Outputs the index of the first element for which p outputs true.
     */
diff --git a/chiselFrontend/src/main/scala/chisel3/core/Bits.scala b/chiselFrontend/src/main/scala/chisel3/core/Bits.scala
index e8aae578..3580b5f3 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Bits.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Bits.scala
@@ -270,9 +270,9 @@ sealed abstract class Bits(width: Width, override val litArg: Option[LitArg])
 
   def do_toBool(implicit sourceInfo: SourceInfo): Bool = {
     width match {
-    case KnownWidth(1) => this(0)
-    case _ => throwException(s"can't covert UInt<$width> to Bool")
-  }
+      case KnownWidth(1) => this(0)
+      case _ => throwException(s"can't covert UInt<$width> to Bool")
+    }
   }
 
   /** Returns this wire concatenated with `other`, where this wire forms the
@@ -407,8 +407,8 @@ sealed class UInt private[core] (width: Width, lit: Option[ULit] = None)
   final def unary_- (): UInt = macro SourceInfoTransform.noArg
   final def unary_-% (): UInt = macro SourceInfoTransform.noArg
 
-  def do_unary_- (implicit sourceInfo: SourceInfo) : UInt = UInt(0) - this
-  def do_unary_-% (implicit sourceInfo: SourceInfo): UInt = UInt(0) -% this
+  def do_unary_- (implicit sourceInfo: SourceInfo) : UInt = UInt.Lit(0) - this
+  def do_unary_-% (implicit sourceInfo: SourceInfo): UInt = UInt.Lit(0) -% this
 
   override def do_+ (that: UInt)(implicit sourceInfo: SourceInfo): UInt = this +% that
   override def do_- (that: UInt)(implicit sourceInfo: SourceInfo): UInt = this -% that
@@ -456,8 +456,8 @@ sealed class UInt private[core] (width: Width, lit: Option[ULit] = None)
   final def andR(): Bool = macro SourceInfoTransform.noArg
   final def xorR(): Bool = macro SourceInfoTransform.noArg
 
-  def do_orR(implicit sourceInfo: SourceInfo): Bool = this != UInt(0)
-  def do_andR(implicit sourceInfo: SourceInfo): Bool = ~this === UInt(0)
+  def do_orR(implicit sourceInfo: SourceInfo): Bool = this != UInt.Lit(0)
+  def do_andR(implicit sourceInfo: SourceInfo): Bool = ~this === UInt.Lit(0)
   def do_xorR(implicit sourceInfo: SourceInfo): Bool = redop(sourceInfo, XorReduceOp)
 
   override def do_< (that: UInt)(implicit sourceInfo: SourceInfo): Bool = compop(sourceInfo, LessOp, that)
@@ -523,14 +523,25 @@ private[core] sealed trait UIntFactory {
   /** Create a UInt port with specified width. */
   def apply(width: Width): UInt = new UInt(width)
   /** Create a UInt with a specified width - compatibility with Chisel2. */
+  def width(width: Int): UInt = apply(Width(width))
+  /** Create a UInt port with specified width. */
+  def width(width: Width): UInt = new UInt(width)
+  /** Create a UInt with a specified width - compatibility with Chisel2. */
   def apply(dummy: Direction, width: Int): UInt = apply(Width(width))
   /** Create a UInt literal with fixed width. */
-  def apply(value: BigInt, width: Int): UInt = apply(value, Width(width))
+  def apply(value: BigInt, width: Int): UInt = Lit(value, Width(width))
   /** Create a UInt literal with inferred width. */
-  def apply(n: String): UInt = apply(parse(n), parsedWidth(n))
-  /** Create a UInt literal with fixed width. */
+  def apply(n: String): UInt = Lit(n)
   /** Create a UInt literal with specified width. */
-  def apply(value: BigInt, width: Width): UInt = {
+  def apply(value: BigInt, width: Width): UInt = Lit(value, width)
+  def Lit(value: BigInt, width: Int): UInt = Lit(value, Width(width))
+   /** Create a UInt literal with inferred width. */
+  def Lit(value: BigInt): UInt = Lit(value, Width())
+  def Lit(n: String): UInt = Lit(parse(n), parsedWidth(n))
+   /** Create a UInt literal with fixed width. */
+  def Lit(n: String, width: Int): UInt = Lit(parse(n), width)
+   /** Create a UInt literal with specified width. */
+  def Lit(value: BigInt, width: Width): UInt = {
     val lit = ULit(value, width)
     val result = new UInt(lit.width, Some(lit))
     // Bind result to being an Literal
@@ -575,8 +586,8 @@ sealed class SInt private (width: Width, lit: Option[SLit] = None)
   final def unary_- (): SInt = macro SourceInfoTransform.noArg
   final def unary_-% (): SInt = macro SourceInfoTransform.noArg
 
-  def unary_- (implicit sourceInfo: SourceInfo): SInt = SInt(0) - this
-  def unary_-% (implicit sourceInfo: SourceInfo): SInt = SInt(0) -% this
+  def unary_- (implicit sourceInfo: SourceInfo): SInt = SInt.Lit(0) - this
+  def unary_-% (implicit sourceInfo: SourceInfo): SInt = SInt.Lit(0) -% this
 
   /** add (default - no growth) operator */
   override def do_+ (that: SInt)(implicit sourceInfo: SourceInfo): SInt =
@@ -643,7 +654,7 @@ sealed class SInt private (width: Width, lit: Option[SLit] = None)
 
   final def abs(): UInt = macro SourceInfoTransform.noArg
 
-  def do_abs(implicit sourceInfo: SourceInfo): UInt = Mux(this < SInt(0), (-this).asUInt, this.asUInt)
+  def do_abs(implicit sourceInfo: SourceInfo): UInt = Mux(this < SInt.Lit(0), (-this).asUInt, this.asUInt)
 
   override def do_<< (that: Int)(implicit sourceInfo: SourceInfo): SInt =
     binop(sourceInfo, SInt(this.width + that), ShiftLeftOp, that)
@@ -669,14 +680,24 @@ object SInt {
   def apply(width: Int): SInt = apply(Width(width))
   /** Create an SInt type with specified width. */
   def apply(width: Width): SInt = new SInt(width)
+  /** Create a SInt type or port with fixed width. */
+  def width(width: Int): SInt = apply(Width(width))
+  /** Create an SInt type with specified width. */
+  def width(width: Width): SInt = new SInt(width)
 
   /** Create an SInt literal with inferred width. */
-  def apply(value: BigInt): SInt = apply(value, Width())
+  def apply(value: BigInt): SInt = Lit(value)
   /** Create an SInt literal with fixed width. */
-  def apply(value: BigInt, width: Int): SInt = apply(value, Width(width))
+  def apply(value: BigInt, width: Int): SInt = Lit(value, width)
 
   /** Create an SInt literal with specified width. */
-  def apply(value: BigInt, width: Width): SInt = {
+  def apply(value: BigInt, width: Width): SInt = Lit(value, width)
+
+  def Lit(value: BigInt): SInt = Lit(value, Width())
+  def Lit(value: BigInt, width: Int): SInt = Lit(value, Width(width))
+   /** Create an SInt literal with specified width. */
+  def Lit(value: BigInt, width: Width): SInt = {
+
     val lit = SLit(value, width)
     val result = new SInt(lit.width, Some(lit))
     // Bind result to being an Literal
@@ -737,7 +758,8 @@ object Bool {
 
   /** Creates Bool literal.
    */
-  def apply(x: Boolean): Bool = {
+  def apply(x: Boolean): Bool = Lit(x)
+  def Lit(x: Boolean): Bool = {
     val result = new Bool(Some(ULit(if (x) 1 else 0, Width(1))))
     // Bind result to being an Literal
     result.binding = LitBinding()
@@ -754,7 +776,7 @@ object Mux {
     * @param alt the value chosen when `cond` is false
     * @example
     * {{{
-    * val muxOut = Mux(data_in === UInt(3), UInt(3, 4), UInt(0, 4))
+    * val muxOut = Mux(data_in === UInt.Lit(3), UInt(3, 4), UInt(0, 4))
     * }}}
     */
   def apply[T <: Data](cond: Bool, con: T, alt: T): T = macro MuxTransform.apply[T]
diff --git a/chiselFrontend/src/main/scala/chisel3/core/Mem.scala b/chiselFrontend/src/main/scala/chisel3/core/Mem.scala
index a9854362..a4e6bee3 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Mem.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Mem.scala
@@ -36,7 +36,7 @@ sealed abstract class MemBase[T <: Data](t: T, val length: Int) extends HasId wi
   /** Creates a read accessor into the memory with static addressing. See the
     * class documentation of the memory for more detailed information.
     */
-  def apply(idx: Int): T = apply(UInt(idx))
+  def apply(idx: Int): T = apply(UInt.Lit(idx))
 
   /** Creates a read/write accessor into the memory with dynamic addressing.
     * See the class documentation of the memory for more detailed information.
diff --git a/chiselFrontend/src/main/scala/chisel3/core/SeqUtils.scala b/chiselFrontend/src/main/scala/chisel3/core/SeqUtils.scala
index 91cb9e89..c1ec6b90 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/SeqUtils.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/SeqUtils.scala
@@ -25,11 +25,11 @@ private[chisel3] object SeqUtils {
 
   def do_count(in: Seq[Bool])(implicit sourceInfo: SourceInfo): UInt = {
     if (in.size == 0) {
-      UInt(0)
+      UInt.Lit(0)
     } else if (in.size == 1) {
       in.head
     } else {
-      count(in.slice(0, in.size/2)) + (UInt(0) ## count(in.slice(in.size/2, in.size)))
+      count(in.slice(0, in.size/2)) + (UInt.Lit(0) ## count(in.slice(in.size/2, in.size)))
     }
   }
 
diff --git a/chiselFrontend/src/main/scala/chisel3/core/When.scala b/chiselFrontend/src/main/scala/chisel3/core/When.scala
index 196e7903..7049eb82 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/When.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/When.scala
@@ -18,9 +18,9 @@ object when {  // scalastyle:ignore object.name
     *
     * @example
     * {{{
-    * when ( myData === UInt(3) ) {
+    * when ( myData === UInt.Lit(3) ) {
     *   // Some logic to run when myData equals 3.
-    * } .elsewhen ( myData === UInt(1) ) {
+    * } .elsewhen ( myData === UInt.Lit(1) ) {
     *   // Some logic to run when myData equals 1.
     * } .otherwise {
     *   // Some logic to run when myData is neither 3 nor 1.