Add support for clock and reset scoping (#509)

withClockAndReset, withReset, and withClock allow changing the implicit clock and reset.
Module.clock and Module.reset provide access to the current implicit clock and reset.

1 files changed, 3 insertions, 3 deletions

diff --git a/chiselFrontend/src/main/scala/chisel3/core/Mem.scala b/chiselFrontend/src/main/scala/chisel3/core/Mem.scala
index ca416b1e..a48af15a 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Mem.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Mem.scala
@@ -27,7 +27,7 @@ object Mem {
     // TODO(twigg): Remove need for this Binding
 
     val mem = new Mem(mt, size)
-    pushCommand(DefMemory(sourceInfo, mem, mt, size)) // TODO multi-clock
+    pushCommand(DefMemory(sourceInfo, mem, mt, size))
     mem
   }
 }
@@ -92,7 +92,7 @@ sealed abstract class MemBase[T <: Data](t: T, val length: Int) extends HasId wi
 
     val port = pushCommand(
       DefMemPort(sourceInfo,
-       t.chiselCloneType, Node(this), dir, i.ref, Node(i._parent.get.clock))
+       t.chiselCloneType, Node(this), dir, i.ref, Node(Builder.forcedClock))
     ).id
     // Bind each element of port to being a MemoryPort
     Binding.bind(port, MemoryPortBinder(Builder.forcedModule), "Error: Fresh t")
@@ -128,7 +128,7 @@ object SyncReadMem {
     // TODO(twigg): Remove need for this Binding
 
     val mem = new SyncReadMem(mt, size)
-    pushCommand(DefSeqMemory(sourceInfo, mem, mt, size)) // TODO multi-clock
+    pushCommand(DefSeqMemory(sourceInfo, mem, mt, size))
     mem
   }
 }