diff options
| author | ducky | 2016-11-16 18:31:24 -0800 |
|---|---|---|
| committer | ducky | 2016-11-21 13:26:56 -0800 |
| commit | 15a8d3818a1b185051b260ffc82da1fb4a60a45e (patch) | |
| tree | ccfc4e7cb11f9ef5e367c28b721a630e27abd51e /chiselFrontend/src/main/scala/chisel3/core/Mem.scala | |
| parent | cd6eb41275381a4399a8a88c886110d276bb805c (diff) | |
Break out deprecated literal constructors, refactor all the things!
Diffstat (limited to 'chiselFrontend/src/main/scala/chisel3/core/Mem.scala')
| -rw-r--r-- | chiselFrontend/src/main/scala/chisel3/core/Mem.scala | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/chiselFrontend/src/main/scala/chisel3/core/Mem.scala b/chiselFrontend/src/main/scala/chisel3/core/Mem.scala index a43b19fe..1863e921 100644 --- a/chiselFrontend/src/main/scala/chisel3/core/Mem.scala +++ b/chiselFrontend/src/main/scala/chisel3/core/Mem.scala @@ -40,7 +40,7 @@ sealed abstract class MemBase[T <: Data](t: T, val length: Int) extends HasId wi */ def apply(idx: Int): T = { require(idx >= 0 && idx < length) - apply(UInt(idx)) + apply(idx.asUInt) } /** Creates a read/write accessor into the memory with dynamic addressing. |