diff options
7 files changed, 167 insertions, 144 deletions
diff --git a/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala b/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala index de7af462..77a1b57a 100644 --- a/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala +++ b/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala @@ -123,10 +123,10 @@ object Vec { /** Truncate an index to implement modulo-power-of-2 addressing. */ private[core] def truncateIndex(idx: UInt, n: Int)(implicit sourceInfo: SourceInfo): UInt = { val w = BigInt(n-1).bitLength - if (n <= 1) UInt(0) + if (n <= 1) 0.U else if (idx.width.known && idx.width.get <= w) idx else if (idx.width.known) idx(w-1,0) - else (idx | UInt(0, w))(w-1,0) + else (idx | 0.U(w))(w-1,0) } } @@ -249,7 +249,7 @@ trait VecLike[T <: Data] extends collection.IndexedSeq[T] with HasId { // IndexedSeq has its own hashCode/equals that we must not use override def hashCode: Int = super[HasId].hashCode override def equals(that: Any): Boolean = super[HasId].equals(that) - + @deprecated("Use Vec.apply instead", "chisel3") def read(idx: UInt): T @@ -288,7 +288,7 @@ trait VecLike[T <: Data] extends collection.IndexedSeq[T] with HasId { /** Helper function that appends an index (literal value) to each element, * useful for hardware generators which output an index. */ - private def indexWhereHelper(p: T => Bool) = this map p zip (0 until length).map(i => UInt(i)) + private def indexWhereHelper(p: T => Bool) = this map p zip (0 until length).map(i => i.asUInt) /** Outputs the index of the first element for which p outputs true. */ @@ -388,7 +388,7 @@ class Bundle extends Aggregate { private[chisel3] lazy val flatten = namedElts.flatMap(_._2.flatten) private[chisel3] override def _onModuleClose: Unit = // scalastyle:ignore method.name for ((name, elt) <- namedElts) { elt.setRef(this, _namespace.name(name)) } - + private[chisel3] final def allElements: Seq[Element] = namedElts.flatMap(_._2.allElements) override def cloneType : this.type = { diff --git a/chiselFrontend/src/main/scala/chisel3/core/Bits.scala b/chiselFrontend/src/main/scala/chisel3/core/Bits.scala index 82b60a4c..1d3f9243 100644 --- a/chiselFrontend/src/main/scala/chisel3/core/Bits.scala +++ b/chiselFrontend/src/main/scala/chisel3/core/Bits.scala @@ -134,7 +134,7 @@ sealed abstract class Bits(width: Width, override val litArg: Option[LitArg]) } val w = x - y + 1 if (isLit()) { - UInt((litValue >> y) & ((BigInt(1) << w) - 1), w) + ((litValue >> y) & ((BigInt(1) << w) - 1)).asUInt(w) } else { Binding.checkSynthesizable(this, s"'this' ($this)") pushOp(DefPrim(sourceInfo, UInt(Width(w)), BitsExtractOp, this.ref, ILit(x), ILit(y))) @@ -304,11 +304,6 @@ sealed abstract class Bits(width: Width, override val litArg: Option[LitArg]) final def toPrintable: Printable = Decimal(this) } -/** Provides a set of operations to create UInt types and literals. - * Identical in functionality to the UInt companion object. - */ -object Bits extends UIntFactory - // REVIEW TODO: Further discussion needed on what Num actually is. /** Abstract trait defining operations available on numeric-like wire data * types. @@ -408,14 +403,14 @@ sealed class UInt private[core] (width: Width, lit: Option[ULit] = None) private[chisel3] def toType = s"UInt$width" override private[chisel3] def fromInt(value: BigInt, width: Int): this.type = - UInt(value, width).asInstanceOf[this.type] + value.asUInt(width).asInstanceOf[this.type] // TODO: refactor to share documentation with Num or add independent scaladoc final def unary_- (): UInt = macro SourceInfoTransform.noArg final def unary_-% (): UInt = macro SourceInfoTransform.noArg - def do_unary_- (implicit sourceInfo: SourceInfo) : UInt = UInt(0) - this - def do_unary_-% (implicit sourceInfo: SourceInfo): UInt = UInt(0) -% this + def do_unary_- (implicit sourceInfo: SourceInfo) : UInt = 0.U - this + def do_unary_-% (implicit sourceInfo: SourceInfo): UInt = 0.U -% this override def do_+ (that: UInt)(implicit sourceInfo: SourceInfo): UInt = this +% that override def do_- (that: UInt)(implicit sourceInfo: SourceInfo): UInt = this -% that @@ -463,8 +458,8 @@ sealed class UInt private[core] (width: Width, lit: Option[ULit] = None) final def andR(): Bool = macro SourceInfoTransform.noArg final def xorR(): Bool = macro SourceInfoTransform.noArg - def do_orR(implicit sourceInfo: SourceInfo): Bool = this != UInt(0) - def do_andR(implicit sourceInfo: SourceInfo): Bool = ~this === UInt(0) + def do_orR(implicit sourceInfo: SourceInfo): Bool = this != 0.U + def do_andR(implicit sourceInfo: SourceInfo): Bool = ~this === 0.U def do_xorR(implicit sourceInfo: SourceInfo): Bool = redop(sourceInfo, XorReduceOp) override def do_< (that: UInt)(implicit sourceInfo: SourceInfo): Bool = compop(sourceInfo, LessOp, that) @@ -483,7 +478,7 @@ sealed class UInt private[core] (width: Width, lit: Option[ULit] = None) final def unary_! () : Bool = macro SourceInfoTransform.noArg - def do_unary_! (implicit sourceInfo: SourceInfo) : Bool = this === UInt(0, 1) + def do_unary_! (implicit sourceInfo: SourceInfo) : Bool = this === 0.U(1) override def do_<< (that: Int)(implicit sourceInfo: SourceInfo): UInt = binop(sourceInfo, UInt(this.width + that), ShiftLeftOp, that) @@ -501,7 +496,7 @@ sealed class UInt private[core] (width: Width, lit: Option[ULit] = None) final def bitSet(off: UInt, dat: Bool): UInt = macro UIntTransform.bitset def do_bitSet(off: UInt, dat: Bool)(implicit sourceInfo: SourceInfo): UInt = { - val bit = UInt(1, 1) << off + val bit = 1.U(1) << off Mux(dat, this | bit, ~(~this | bit)) } @@ -532,31 +527,20 @@ sealed class UInt private[core] (width: Width, lit: Option[ULit] = None) } // This is currently a factory because both Bits and UInt inherit it. -private[core] sealed trait UIntFactory { +trait UIntFactory { /** Create a UInt type with inferred width. */ def apply(): UInt = apply(Width()) /** Create a UInt port with specified width. */ def apply(width: Width): UInt = new UInt(width) - /** Create a UInt with a specified width - compatibility with Chisel2. */ - def width(width: Int): UInt = apply(Width(width)) - /** Create a UInt port with specified width. */ - def width(width: Width): UInt = new UInt(width) - /** Create a UInt literal with fixed width. */ - def apply(value: BigInt, width: Int): UInt = Lit(value, Width(width)) - /** Create a UInt literal with inferred width. */ - def apply(n: String): UInt = Lit(n) - /** Create a UInt literal with fixed width. */ - def apply(n: String, width: Int): UInt = Lit(parse(n), width) - /** Create a UInt literal with specified width. */ - def apply(value: BigInt, width: Width): UInt = Lit(value, width) - def Lit(value: BigInt, width: Int): UInt = Lit(value, Width(width)) + + protected[chisel3] def Lit(value: BigInt, width: Int): UInt = Lit(value, Width(width)) /** Create a UInt literal with inferred width. */ - def Lit(value: BigInt): UInt = Lit(value, Width()) - def Lit(n: String): UInt = Lit(parse(n), parsedWidth(n)) + protected[chisel3] def Lit(value: BigInt): UInt = Lit(value, Width()) + protected[chisel3] def Lit(n: String): UInt = Lit(parse(n), parsedWidth(n)) /** Create a UInt literal with fixed width. */ - def Lit(n: String, width: Int): UInt = Lit(parse(n), width) + protected[chisel3] def Lit(n: String, width: Int): UInt = Lit(parse(n), width) /** Create a UInt literal with specified width. */ - def Lit(value: BigInt, width: Width): UInt = { + protected[chisel3] def Lit(value: BigInt, width: Width): UInt = { val lit = ULit(value, width) val result = new UInt(lit.width, Some(lit)) // Bind result to being an Literal @@ -572,25 +556,7 @@ private[core] sealed trait UIntFactory { apply(KnownUIntRange(range._1, range._2)) } - /** Create a UInt with a specified width - compatibility with Chisel2. */ - // NOTE: This resolves UInt(width = 32) - def apply(dir: Option[Direction] = None, width: Int): UInt = apply(Width(width)) - /** Create a UInt literal with inferred width.- compatibility with Chisel2. */ - def apply(value: BigInt): UInt = apply(value, Width()) - /** Create a UInt with a specified direction and width - compatibility with Chisel2. */ - def apply(dir: Direction, width: Int): UInt = apply(dir, Width(width)) - /** Create a UInt with a specified direction, but unspecified width - compatibility with Chisel2. */ - def apply(dir: Direction): UInt = apply(dir, Width()) - def apply(dir: Direction, wWidth: Width): UInt = { - val result = apply(wWidth) - dir match { - case Direction.Input => Input(result) - case Direction.Output => Output(result) - case Direction.Unspecified => result - } - } - - private def parse(n: String) = { + protected def parse(n: String) = { val (base, num) = n.splitAt(1) val radix = base match { case "x" | "h" => 16 @@ -602,7 +568,7 @@ private[core] sealed trait UIntFactory { BigInt(num.filterNot(_ == '_'), radix) } - private def parsedWidth(n: String) = + protected def parsedWidth(n: String) = if (n(0) == 'b') { Width(n.length-1) } else if (n(0) == 'h') { @@ -613,6 +579,7 @@ private[core] sealed trait UIntFactory { } object UInt extends UIntFactory +object Bits extends UIntFactory sealed class SInt private (width: Width, lit: Option[SLit] = None) extends Bits(width, lit) with Num[SInt] { diff --git a/chiselFrontend/src/main/scala/chisel3/core/Mem.scala b/chiselFrontend/src/main/scala/chisel3/core/Mem.scala index a43b19fe..1863e921 100644 --- a/chiselFrontend/src/main/scala/chisel3/core/Mem.scala +++ b/chiselFrontend/src/main/scala/chisel3/core/Mem.scala @@ -40,7 +40,7 @@ sealed abstract class MemBase[T <: Data](t: T, val length: Int) extends HasId wi */ def apply(idx: Int): T = { require(idx >= 0 && idx < length) - apply(UInt(idx)) + apply(idx.asUInt) } /** Creates a read/write accessor into the memory with dynamic addressing. diff --git a/chiselFrontend/src/main/scala/chisel3/core/SeqUtils.scala b/chiselFrontend/src/main/scala/chisel3/core/SeqUtils.scala index 558dea7a..da4f2d94 100644 --- a/chiselFrontend/src/main/scala/chisel3/core/SeqUtils.scala +++ b/chiselFrontend/src/main/scala/chisel3/core/SeqUtils.scala @@ -30,7 +30,7 @@ private[chisel3] object SeqUtils { def count(in: Seq[Bool]): UInt = macro SourceInfoTransform.inArg def do_count(in: Seq[Bool])(implicit sourceInfo: SourceInfo): UInt = in.size match { - case 0 => UInt(0) + case 0 => 0.U case 1 => in.head case n => count(in take n/2) +& count(in drop n/2) } @@ -57,7 +57,7 @@ private[chisel3] object SeqUtils { if (in.tail.isEmpty) { in.head._2 } else { - val masked = for ((s, i) <- in) yield Mux(s, i.asUInt, UInt(0)) + val masked = for ((s, i) <- in) yield Mux(s, i.asUInt, 0.U) val width = in.map(_._2.width).reduce(_ max _) in.head._2.cloneTypeWidth(width).fromBits(masked.reduceLeft(_|_)) } diff --git a/chiselFrontend/src/main/scala/chisel3/core/package.scala b/chiselFrontend/src/main/scala/chisel3/core/package.scala new file mode 100644 index 00000000..46dfbe20 --- /dev/null +++ b/chiselFrontend/src/main/scala/chisel3/core/package.scala @@ -0,0 +1,50 @@ +package chisel3 { + package object core { + import internal.firrtl.Width + + /** + * These implicit classes allow one to convert scala.Int|scala.BigInt to + * Chisel.UInt|Chisel.SInt by calling .asUInt|.asSInt on them, respectively. + * The versions .asUInt(width)|.asSInt(width) are also available to explicitly + * mark a width for the new literal. + * + * Also provides .asBool to scala.Boolean and .asUInt to String + * + * Note that, for stylistic reasons, one should avoid extracting immediately + * after this call using apply, ie. 0.asUInt(1)(0) due to potential for + * confusion (the 1 is a bit length and the 0 is a bit extraction position). + * Prefer storing the result and then extracting from it. + */ + implicit class fromIntToLiteral(val x: Int) { + def U: UInt = UInt.Lit(BigInt(x), Width()) // scalastyle:ignore method.name + def S: SInt = SInt(BigInt(x), Width()) // scalastyle:ignore method.name + + def asUInt(): UInt = UInt.Lit(x, Width()) + def asSInt(): SInt = SInt(x, Width()) + def asUInt(width: Int): UInt = UInt.Lit(x, width) + def asSInt(width: Int): SInt = SInt(x, width) + } + + implicit class fromBigIntToLiteral(val x: BigInt) { + def U: UInt = UInt.Lit(x, Width()) // scalastyle:ignore method.name + def S: SInt = SInt(x, Width()) // scalastyle:ignore method.name + + def asUInt(): UInt = UInt.Lit(x, Width()) + def asSInt(): SInt = SInt(x, Width()) + def asUInt(width: Int): UInt = UInt.Lit(x, width) + def asSInt(width: Int): SInt = SInt(x, width) + } + + implicit class fromStringToLiteral(val x: String) { + def U: UInt = UInt.Lit(x) // scalastyle:ignore method.name + } + + implicit class fromBooleanToLiteral(val x: Boolean) { + def B: Bool = Bool(x) // scalastyle:ignore method.name + } + + implicit class fromDoubleToLiteral(val x: Double) { + def F(binaryPoint: Int): FixedPoint = FixedPoint.fromDouble(x, binaryPoint = binaryPoint) + } + } +}
\ No newline at end of file diff --git a/src/main/scala/chisel3/compatibility.scala b/src/main/scala/chisel3/compatibility.scala index d0d2ddb4..7157b4d4 100644 --- a/src/main/scala/chisel3/compatibility.scala +++ b/src/main/scala/chisel3/compatibility.scala @@ -6,6 +6,7 @@ package object Chisel { // scalastyle:ignore package.object.name implicit val defaultCompileOptions = chisel3.core.ExplicitCompileOptions.NotStrict type Direction = chisel3.core.Direction + val INPUT = chisel3.core.Direction.Input val OUTPUT = chisel3.core.Direction.Output val NODIR = chisel3.core.Direction.Unspecified @@ -38,12 +39,51 @@ package object Chisel { // scalastyle:ignore package.object.name val assert = chisel3.core.assert val stop = chisel3.core.stop + trait UIntFactory extends chisel3.core.UIntFactory { + import chisel3.internal.firrtl.Width + + /** Create a UInt with a specified width */ + def width(width: Int): UInt = apply(Width(width)) + + /** Create a UInt literal with inferred width. */ + def apply(n: String): UInt = Lit(n) + /** Create a UInt literal with fixed width. */ + def apply(n: String, width: Int): UInt = Lit(parse(n), width) + + /** Create a UInt literal with specified width. */ + def apply(value: BigInt, width: Width): UInt = Lit(value, width) + + /** Create a UInt literal with fixed width. */ + def apply(value: BigInt, width: Int): UInt = Lit(value, Width(width)) + + /** Create a UInt with a specified width - compatibility with Chisel2. */ + // NOTE: This resolves UInt(width = 32) + def apply(dir: Option[Direction] = None, width: Int): UInt = apply(Width(width)) + /** Create a UInt literal with inferred width.- compatibility with Chisel2. */ + def apply(value: BigInt): UInt = apply(value, Width()) + /** Create a UInt with a specified direction and width - compatibility with Chisel2. */ + def apply(dir: Direction, width: Int): UInt = apply(dir, Width(width)) + /** Create a UInt with a specified direction, but unspecified width - compatibility with Chisel2. */ + def apply(dir: Direction): UInt = apply(dir, Width()) + def apply(dir: Direction, wWidth: Width): UInt = { + val result = apply(wWidth) + dir match { + case chisel3.core.Direction.Input => chisel3.core.Input(result) + case chisel3.core.Direction.Output => chisel3.core.Output(result) + case chisel3.core.Direction.Unspecified => result + } + } + + /** Create a UInt port with specified width. */ + def width(width: Width): UInt = apply(width) + } + type Element = chisel3.core.Element type Bits = chisel3.core.Bits - val Bits = chisel3.core.Bits + object Bits extends UIntFactory type Num[T <: Data] = chisel3.core.Num[T] type UInt = chisel3.core.UInt - val UInt = chisel3.core.UInt + object UInt extends UIntFactory type SInt = chisel3.core.SInt val SInt = chisel3.core.SInt type Bool = chisel3.core.Bool @@ -68,46 +108,10 @@ package object Chisel { // scalastyle:ignore package.object.name val when = chisel3.core.when type WhenContext = chisel3.core.WhenContext - import chisel3.internal.firrtl.Width - /** - * These implicit classes allow one to convert scala.Int|scala.BigInt to - * Chisel.UInt|Chisel.SInt by calling .asUInt|.asSInt on them, respectively. - * The versions .asUInt(width)|.asSInt(width) are also available to explicitly - * mark a width for the new literal. - * - * Also provides .asBool to scala.Boolean and .asUInt to String - * - * Note that, for stylistic reasons, one should avoid extracting immediately - * after this call using apply, ie. 0.asUInt(1)(0) due to potential for - * confusion (the 1 is a bit length and the 0 is a bit extraction position). - * Prefer storing the result and then extracting from it. - */ - implicit class fromIntToLiteral(val x: Int) extends AnyVal { - def U: UInt = UInt(BigInt(x), Width()) // scalastyle:ignore method.name - def S: SInt = SInt(BigInt(x), Width()) // scalastyle:ignore method.name - - def asUInt(): UInt = UInt(x, Width()) - def asSInt(): SInt = SInt(x, Width()) - def asUInt(width: Int): UInt = UInt(x, width) - def asSInt(width: Int): SInt = SInt(x, width) - } - - implicit class fromBigIntToLiteral(val x: BigInt) extends AnyVal { - def U: UInt = UInt(x, Width()) // scalastyle:ignore method.name - def S: SInt = SInt(x, Width()) // scalastyle:ignore method.name - - def asUInt(): UInt = UInt(x, Width()) - def asSInt(): SInt = SInt(x, Width()) - def asUInt(width: Int): UInt = UInt(x, width) - def asSInt(width: Int): SInt = SInt(x, width) - } - implicit class fromStringToLiteral(val x: String) extends AnyVal { - def U: UInt = UInt(x) // scalastyle:ignore method.name - } - implicit class fromBooleanToLiteral(val x: Boolean) extends AnyVal { - def B: Bool = Bool(x) // scalastyle:ignore method.name - } - + implicit class fromtIntToLiteral(override val x: Int) extends chisel3.core.fromIntToLiteral(x) + implicit class fromBigIntToLiteral(override val x: BigInt) extends chisel3.core.fromBigIntToLiteral(x) + implicit class fromStringToLiteral(override val x: String) extends chisel3.core.fromStringToLiteral(x) + implicit class fromBooleanToLiteral(override val x: Boolean) extends chisel3.core.fromBooleanToLiteral(x) type BackendCompilationUtilities = chisel3.BackendCompilationUtilities val Driver = chisel3.Driver diff --git a/src/main/scala/chisel3/package.scala b/src/main/scala/chisel3/package.scala index 29aa6528..07dcdaca 100644 --- a/src/main/scala/chisel3/package.scala +++ b/src/main/scala/chisel3/package.scala @@ -31,10 +31,48 @@ package object chisel3 { // scalastyle:ignore package.object.name type Element = chisel3.core.Element type Bits = chisel3.core.Bits - val Bits = chisel3.core.Bits + + trait UIntFactory extends chisel3.core.UIntFactory { + /** Create a UInt with a specified width */ + def width(width: Int): UInt = apply(Width(width)) + + /** Create a UInt literal with inferred width. */ + def apply(n: String): UInt = Lit(n) + /** Create a UInt literal with fixed width. */ + def apply(n: String, width: Int): UInt = Lit(parse(n), width) + + /** Create a UInt literal with specified width. */ + def apply(value: BigInt, width: Width): UInt = Lit(value, width) + + /** Create a UInt literal with fixed width. */ + def apply(value: BigInt, width: Int): UInt = Lit(value, Width(width)) + + /** Create a UInt with a specified width - compatibility with Chisel2. */ + // NOTE: This resolves UInt(width = 32) + def apply(dir: Option[Direction] = None, width: Int): UInt = apply(Width(width)) + /** Create a UInt literal with inferred width.- compatibility with Chisel2. */ + def apply(value: BigInt): UInt = apply(value, Width()) + /** Create a UInt with a specified direction and width - compatibility with Chisel2. */ + def apply(dir: Direction, width: Int): UInt = apply(dir, Width(width)) + /** Create a UInt with a specified direction, but unspecified width - compatibility with Chisel2. */ + def apply(dir: Direction): UInt = apply(dir, Width()) + def apply(dir: Direction, wWidth: Width): UInt = { + val result = apply(wWidth) + dir match { + case chisel3.core.Direction.Input => Input(result) + case chisel3.core.Direction.Output => Output(result) + case chisel3.core.Direction.Unspecified => result + } + } + + /** Create a UInt port with specified width. */ + def width(width: Width): UInt = apply(width) + } + + object Bits extends UIntFactory type Num[T <: Data] = chisel3.core.Num[T] type UInt = chisel3.core.UInt - val UInt = chisel3.core.UInt + object UInt extends UIntFactory type SInt = chisel3.core.SInt val SInt = chisel3.core.SInt type FixedPoint = chisel3.core.FixedPoint @@ -113,48 +151,12 @@ package object chisel3 { // scalastyle:ignore package.object.name implicit def string2Printable(str: String): Printable = PString(str) - /** - * These implicit classes allow one to convert scala.Int|scala.BigInt to - * Chisel.UInt|Chisel.SInt by calling .asUInt|.asSInt on them, respectively. - * The versions .asUInt(width)|.asSInt(width) are also available to explicitly - * mark a width for the new literal. - * - * Also provides .asBool to scala.Boolean and .asUInt to String - * - * Note that, for stylistic reasons, one should avoid extracting immediately - * after this call using apply, ie. 0.asUInt(1)(0) due to potential for - * confusion (the 1 is a bit length and the 0 is a bit extraction position). - * Prefer storing the result and then extracting from it. - */ - implicit class fromIntToLiteral(val x: Int) extends AnyVal { - def U: UInt = UInt(BigInt(x), Width()) // scalastyle:ignore method.name - def S: SInt = SInt(BigInt(x), Width()) // scalastyle:ignore method.name - - def asUInt(): UInt = UInt(x, Width()) - def asSInt(): SInt = SInt(x, Width()) - def asUInt(width: Int): UInt = UInt(x, width) - def asSInt(width: Int): SInt = SInt(x, width) - } + implicit class fromtIntToLiteral(override val x: Int) extends chisel3.core.fromIntToLiteral(x) + implicit class fromBigIntToLiteral(override val x: BigInt) extends chisel3.core.fromBigIntToLiteral(x) + implicit class fromStringToLiteral(override val x: String) extends chisel3.core.fromStringToLiteral(x) + implicit class fromBooleanToLiteral(override val x: Boolean) extends chisel3.core.fromBooleanToLiteral(x) + implicit class fromDoubleToLiteral(override val x: Double) extends chisel3.core.fromDoubleToLiteral(x) - implicit class fromBigIntToLiteral(val x: BigInt) extends AnyVal { - def U: UInt = UInt(x, Width()) // scalastyle:ignore method.name - def S: SInt = SInt(x, Width()) // scalastyle:ignore method.name - - def asUInt(): UInt = UInt(x, Width()) - def asSInt(): SInt = SInt(x, Width()) - def asUInt(width: Int): UInt = UInt(x, width) - def asSInt(width: Int): SInt = SInt(x, width) - } - implicit class fromStringToLiteral(val x: String) extends AnyVal { - def U: UInt = UInt(x) // scalastyle:ignore method.name - } - implicit class fromBooleanToLiteral(val x: Boolean) extends AnyVal { - def B: Bool = Bool(x) // scalastyle:ignore method.name - } - - implicit class fromDoubleToLiteral(val x: Double) extends AnyVal { - def F(binaryPoint: Int): FixedPoint = FixedPoint.fromDouble(x, binaryPoint = binaryPoint) - } implicit class fromUIntToBitPatComparable(val x: UInt) extends AnyVal { final def === (that: BitPat): Bool = macro SourceInfoTransform.thatArg |