Merge in "complete" versions of Mem, Reg.

1 files changed, 22 insertions, 9 deletions

diff --git a/chiselFrontend/src/main/scala/chisel3/core/Mem.scala b/chiselFrontend/src/main/scala/chisel3/core/Mem.scala
index 38f5ef14..5c1b5976 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Mem.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Mem.scala
@@ -19,9 +19,11 @@ object Mem {
     * @param t data type of memory element
     */
   def apply[T <: Data](size: Int, t: T): Mem[T] = macro MemTransform.apply[T]
-
   def do_apply[T <: Data](size: Int, t: T)(implicit sourceInfo: SourceInfo): Mem[T] = {
-    val mt  = t.cloneType
+    val mt  = t.newType
+    Binding.bind(mt, NoDirectionBinder, "Error: fresh t")
+    // TODO(twigg): Remove need for this Binding
+
     val mem = new Mem(mt, size)
     pushCommand(DefMemory(sourceInfo, mem, mt, size)) // TODO multi-clock
     mem
@@ -60,7 +62,7 @@ sealed abstract class MemBase[T <: Data](t: T, val length: Int) extends HasId wi
     *
     * @param idx memory element index to write into
     * @param data new data to write
-    * @param mask write mask as a Vec of Bool: a write to the Vec element in
+    * @param mask write mask as a Seq of Bool: a write to the Vec element in
     * memory is only performed if the corresponding mask index is true.
     *
     * @note this is only allowed if the memory's element data type is a Vec
@@ -79,9 +81,17 @@ sealed abstract class MemBase[T <: Data](t: T, val length: Int) extends HasId wi
       when (cond) { port := datum }
   }
 
-  private def makePort(sourceInfo: SourceInfo, idx: UInt, dir: MemPortDirection): T =
-    pushCommand(DefMemPort(sourceInfo,
-        t.cloneType, Node(this), dir, idx.ref, Node(idx._parent.get.clock))).id
+  private def makePort(sourceInfo: SourceInfo, idx: UInt, dir: MemPortDirection): T = {
+    Binding.checkSynthesizable(idx, s"'idx' ($idx)")
+
+    val port = pushCommand(
+      DefMemPort(sourceInfo,
+       t.newType, Node(this), dir, idx.ref, Node(idx._parent.get.clock))
+    ).id
+    // Bind each element of port to being a MemoryPort
+    Binding.bind(port, MemoryPortBinder(Builder.forcedModule), "Error: Fresh t")
+    port
+  }
 }
 
 /** A combinational-read, sequential-write memory.
@@ -93,7 +103,7 @@ sealed abstract class MemBase[T <: Data](t: T, val length: Int) extends HasId wi
   * @note when multiple conflicting writes are performed on a Mem element, the
   * result is undefined (unlike Vec, where the last assignment wins)
   */
-sealed class Mem[T <: Data](t: T, length: Int) extends MemBase(t, length)
+final class Mem[T <: Data] private (t: T, length: Int) extends MemBase(t, length)
 
 object SeqMem {
   @deprecated("SeqMem argument order should be size, t; this will be removed by the official release", "chisel3")
@@ -107,7 +117,10 @@ object SeqMem {
   def apply[T <: Data](size: Int, t: T): SeqMem[T] = macro MemTransform.apply[T]
 
   def do_apply[T <: Data](size: Int, t: T)(implicit sourceInfo: SourceInfo): SeqMem[T] = {
-    val mt  = t.cloneType
+    val mt  = t.newType
+    Binding.bind(mt, NoDirectionBinder, "Error: fresh t")
+    // TODO(twigg): Remove need for this Binding
+
     val mem = new SeqMem(mt, size)
     pushCommand(DefSeqMemory(sourceInfo, mem, mt, size)) // TODO multi-clock
     mem
@@ -124,7 +137,7 @@ object SeqMem {
   * @note when multiple conflicting writes are performed on a Mem element, the
   * result is undefined (unlike Vec, where the last assignment wins)
   */
-sealed class SeqMem[T <: Data](t: T, n: Int) extends MemBase[T](t, n) {
+final class SeqMem[T <: Data] private (t: T, n: Int) extends MemBase[T](t, n) {
   def read(addr: UInt, enable: Bool): T = {
     implicit val sourceInfo = UnlocatableSourceInfo
     val a = Wire(UInt())