sfcX - Scala FIRRTL Compiler for chiselX

Age	Commit message (Collapse)	Author
2016-08-15	Remove stanza (#231)	Adam Izraelevitz
	* Removed stanza implementation/tests. In the future we can move the stanza tests over, but for now they should be deleted. * Added back integration .fir files * Added Makefile to give Travis hooks * Added firrtl script (was ignored before)
2016-01-16	WIP. Fixed a bunch of tests. Starting on implementing chirrtl, but hit ↵	azidar
	roadblock in assigning clocked ports
2016-01-16	New memory works with verilog. Slowly changing tests and fixing bugs.	azidar
	Decided to not have Conditionally in low firrtl - instead, Print and Stop have enables
2015-08-24	Changed all tests to use verilog backend.	azidar

2015-07-31	Added errors for bulk connects where field names match but types/flips don't	azidar

2015-07-31	Updated tests to pipe from stderr to stdout	azidar

2015-07-14	Pass most tests. The ones that do not pass are not expected to, yet	azidar

2015-05-27	Added sequential memories. mem no longer exists, must declare either cmem or ↵	azidar
	smem. Added firrtl-gensym utility to generate a hashmap of names
2015-05-26	Added <>. Added additional checks for primops. Added new chisel3 files.	azidar