diff options
| author | azidar | 2015-08-24 11:45:37 -0700 |
|---|---|---|
| committer | azidar | 2015-08-24 11:45:37 -0700 |
| commit | 5d3061bfed8445370e6fa97ec9238ba49e8fafbc (patch) | |
| tree | ba0373c05118215fa332c9e7cd10233a69800f53 /test/features/BulkConnect.fir | |
| parent | 50cf7a4823d69967dcb2b10cdef892b0ab5f2184 (diff) | |
Changed all tests to use verilog backend.
Diffstat (limited to 'test/features/BulkConnect.fir')
| -rw-r--r-- | test/features/BulkConnect.fir | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/test/features/BulkConnect.fir b/test/features/BulkConnect.fir index 9120c4a8..f08d6dc7 100644 --- a/test/features/BulkConnect.fir +++ b/test/features/BulkConnect.fir @@ -1,4 +1,4 @@ -; RUN: firrtl -i %s -o %s.flo -X flo -p c 2>&1 | tee %s.out | FileCheck %s +; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s ;CHECK: Lower To Ground circuit Top : module Top : |