| Age | Commit message (Expand) | Author |
|---|---|---|
| 2016-01-16 | New memory works with verilog. Slowly changing tests and fixing bugs. | azidar |
| 2015-08-26 | Fixed bug where firrtl was incorrectly judging the width of a bigint. #36 #37. | azidar |
| 2015-08-25 | Added width check pass with tests. #22. | azidar |
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index : sfcX | |
| Scala FIRRTL Compiler for chiselX |
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