diff options
| author | azidar | 2015-12-09 18:31:45 -0800 |
|---|---|---|
| committer | azidar | 2016-01-16 14:28:17 -0800 |
| commit | be78d49aa01c097978f69a3b022acb2047fdf438 (patch) | |
| tree | 76dc4b32b5e6861938404ebb4d124ca5b87d13a5 /test/errors/width | |
| parent | c427b31a1ef8361b643d5f7435aeb42472dfe626 (diff) | |
New memory works with verilog. Slowly changing tests and fixing bugs.
Decided to not have Conditionally in low firrtl - instead, Print and
Stop have enables
Diffstat (limited to 'test/errors/width')
| -rw-r--r-- | test/errors/width/NegWidth.fir | 2 | ||||
| -rw-r--r-- | test/errors/width/SmallWidth.fir | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/test/errors/width/NegWidth.fir b/test/errors/width/NegWidth.fir index 5d5bbf43..e02884a8 100644 --- a/test/errors/width/NegWidth.fir +++ b/test/errors/width/NegWidth.fir @@ -6,4 +6,4 @@ circuit Top : output y : UInt wire x : UInt<2> - y := shr(x,4) + y <= shr(x,4) diff --git a/test/errors/width/SmallWidth.fir b/test/errors/width/SmallWidth.fir index 0ee60ec0..0885ba52 100644 --- a/test/errors/width/SmallWidth.fir +++ b/test/errors/width/SmallWidth.fir @@ -5,7 +5,7 @@ circuit Top : module Top : output z : UInt - z := add(UInt<4>("h121"),UInt<3>("h13333")) + z <= add(UInt<4>("h121"),UInt<3>("h13333")) |