Added width check pass with tests. #22.

3 files changed, 34 insertions, 0 deletions

diff --git a/test/errors/width/NegWidth.fir b/test/errors/width/NegWidth.fir
new file mode 100644
index 00000000..5d5bbf43
--- /dev/null
+++ b/test/errors/width/NegWidth.fir
@@ -0,0 +1,9 @@
+; RUN: firrtl -i %s -o %s.v -X verilog -p ciwT 2>&1 | tee %s.out | FileCheck %s
+; CHECK: Width cannot be negative or zero.
+
+circuit Top : 
+  module Top : 
+    output y : UInt
+
+    wire x : UInt<2>
+    y := shr(x,4)
diff --git a/test/errors/width/SmallWidth.fir b/test/errors/width/SmallWidth.fir
new file mode 100644
index 00000000..9e26699e
--- /dev/null
+++ b/test/errors/width/SmallWidth.fir
@@ -0,0 +1,13 @@
+; RUN: firrtl -i %s -o %s.v -X verilog -p ciwT 2>&1 | tee %s.out | FileCheck %s
+; CHECK: Width too small for constant "h121".
+; CHECK: Width too small for constant "h13333".
+
+circuit Top : 
+  module Top : 
+    output z : UInt
+
+    z := add(UInt<4>("h121"),UInt<3>("h13333"))
+
+
+
+
diff --git a/test/errors/width/UninferredWidth.fir b/test/errors/width/UninferredWidth.fir
new file mode 100644
index 00000000..d4cff841
--- /dev/null
+++ b/test/errors/width/UninferredWidth.fir
@@ -0,0 +1,12 @@
+; RUN: firrtl -i %s -o %s.v -X verilog -p ciwTd 2>&1 | tee %s.out | FileCheck %s
+; CHECK: Uninferred width.
+
+circuit Top : 
+  module Top : 
+    input z : UInt
+    
+
+
+
+
+