sfcX - Scala FIRRTL Compiler for chiselX

Age	Commit message (Collapse)	Author
2015-08-24	Removed old chisel3 tests that all failed for syntax reasons. Tests should ↵	azidar
	now be small examples, categorized by either passes, errors, or features.
2015-07-14	Added clock support	azidar

2015-07-14	Pass most tests. The ones that do not pass are not expected to, yet	azidar

2015-06-04	Fixed fir files so they correctly compile to verilog! Front-end needs to ↵	azidar
	generate as-SInt instead of convert, always. Added fast build to Makefile
2015-06-03	Fixed verilog backend bugs. Passes ALU. Fails Datapath	azidar

2015-06-02	Added sequential/combinational memories. Started debugging verilog backend. ↵	azidar
	Added Long support so UInt(LARGENUMBER) works
2015-05-21	Added pad pass, used for flo backend	azidar

2015-05-13	Added source indicators from FIRRTL files. Pass in -p i to get them printed. ↵	azidar
	Should show up with check passes
2015-05-04	Fixed bug where instance types were not lowered	azidar

2015-05-04	Updated stuff	azidar

2015-05-04	Fixed change where type of mux-ss was incorrect	azidar

2015-05-02	Added a infrastructure for check passes, and wrote a few	azidar