diff options
| author | azidar | 2015-07-07 10:13:29 -0700 |
|---|---|---|
| committer | azidar | 2015-07-14 11:29:55 -0700 |
| commit | d696dd01de8a1a83a376c719490f475be991f387 (patch) | |
| tree | ca5d8f21c0f7787cc6eb00e078f0c0ae1e20a182 /test/chisel3/Datapath.fir | |
| parent | 3c8f283b445ca99d4ed4c1e04e2bc8bdcdbd72f6 (diff) | |
Pass most tests. The ones that do not pass are not expected to, yet
Diffstat (limited to 'test/chisel3/Datapath.fir')
| -rw-r--r-- | test/chisel3/Datapath.fir | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/test/chisel3/Datapath.fir b/test/chisel3/Datapath.fir index 7d684395..c2752a37 100644 --- a/test/chisel3/Datapath.fir +++ b/test/chisel3/Datapath.fir @@ -100,19 +100,19 @@ circuit Datapath : cmem regs : UInt<32>[32] node T_495 = eq(raddr1, UInt<1>(0)) node T_496 = bit-not(T_495) - accessor T_497 = regs[raddr1] + infer accessor T_497 = regs[raddr1] node T_498 = mux(T_496, T_497, UInt<1>(0)) rdata1 := T_498 node T_499 = eq(raddr2, UInt<1>(0)) node T_500 = bit-not(T_499) - accessor T_501 = regs[raddr2] + infer accessor T_501 = regs[raddr2] node T_502 = mux(T_500, T_501, UInt<1>(0)) rdata2 := T_502 node T_503 = eq(waddr, UInt<1>(0)) node T_504 = bit-not(T_503) node T_505 = bit-and(wen, T_504) when T_505 : - accessor T_506 = regs[waddr] + infer accessor T_506 = regs[waddr] T_506 := wdata module ImmGenWire : output out : UInt<32> |