Pass most tests. The ones that do not pass are not expected to, yet

10 files changed, 28 insertions, 28 deletions

diff --git a/test/chisel3/Core.fir b/test/chisel3/Core.fir
index 5c446b3d..e9aef65f 100644
--- a/test/chisel3/Core.fir
+++ b/test/chisel3/Core.fir
@@ -100,19 +100,19 @@ circuit Core :
     cmem regs : UInt<32>[32]
     node T_1286 = eq(raddr1, UInt<1>(0))
     node T_1287 = bit-not(T_1286)
-    accessor T_1288 = regs[raddr1]
+    infer accessor T_1288 = regs[raddr1]
     node T_1289 = mux(T_1287, T_1288, UInt<1>(0))
     rdata1 := T_1289
     node T_1290 = eq(raddr2, UInt<1>(0))
     node T_1291 = bit-not(T_1290)
-    accessor T_1292 = regs[raddr2]
+    infer accessor T_1292 = regs[raddr2]
     node T_1293 = mux(T_1291, T_1292, UInt<1>(0))
     rdata2 := T_1293
     node T_1294 = eq(waddr, UInt<1>(0))
     node T_1295 = bit-not(T_1294)
     node T_1296 = bit-and(wen, T_1295)
     when T_1296 : 
-      accessor T_1297 = regs[waddr]
+      infer accessor T_1297 = regs[waddr]
       T_1297 := wdata
   module ImmGenWire : 
     output out : UInt<32>
diff --git a/test/chisel3/Datapath.fir b/test/chisel3/Datapath.fir
index 7d684395..c2752a37 100644
--- a/test/chisel3/Datapath.fir
+++ b/test/chisel3/Datapath.fir
@@ -100,19 +100,19 @@ circuit Datapath :
     cmem regs : UInt<32>[32]
     node T_495 = eq(raddr1, UInt<1>(0))
     node T_496 = bit-not(T_495)
-    accessor T_497 = regs[raddr1]
+    infer accessor T_497 = regs[raddr1]
     node T_498 = mux(T_496, T_497, UInt<1>(0))
     rdata1 := T_498
     node T_499 = eq(raddr2, UInt<1>(0))
     node T_500 = bit-not(T_499)
-    accessor T_501 = regs[raddr2]
+    infer accessor T_501 = regs[raddr2]
     node T_502 = mux(T_500, T_501, UInt<1>(0))
     rdata2 := T_502
     node T_503 = eq(waddr, UInt<1>(0))
     node T_504 = bit-not(T_503)
     node T_505 = bit-and(wen, T_504)
     when T_505 : 
-      accessor T_506 = regs[waddr]
+      infer accessor T_506 = regs[waddr]
       T_506 := wdata
   module ImmGenWire : 
     output out : UInt<32>
diff --git a/test/chisel3/Datapath_new.fir b/test/chisel3/Datapath_new.fir
index 9f018394..2d3072b2 100644
--- a/test/chisel3/Datapath_new.fir
+++ b/test/chisel3/Datapath_new.fir
@@ -96,19 +96,19 @@ circuit Datapath :
     cmem regs : UInt<32>[32]
     node T_485 = eq(raddr1, UInt<1>(0))
     node T_486 = bit-not(T_485)
-    accessor T_487 = regs[raddr1]
+    infer accessor T_487 = regs[raddr1]
     node T_488 = mux(T_486, T_487, UInt<1>(0))
     rdata1 := T_488
     node T_489 = eq(raddr2, UInt<1>(0))
     node T_490 = bit-not(T_489)
-    accessor T_491 = regs[raddr2]
+    infer accessor T_491 = regs[raddr2]
     node T_492 = mux(T_490, T_491, UInt<1>(0))
     rdata2 := T_492
     node T_493 = eq(waddr, UInt<1>(0))
     node T_494 = bit-not(T_493)
     node T_495 = bit-and(wen, T_494)
     when T_495 : 
-      accessor T_496 = regs[waddr]
+      infer accessor T_496 = regs[waddr]
       T_496 := wdata
   module ImmGenWire : 
     output out : UInt<32>
diff --git a/test/chisel3/MemorySearch.fir b/test/chisel3/MemorySearch.fir
index a0cc0b7d..fec082c0 100644
--- a/test/chisel3/MemorySearch.fir
+++ b/test/chisel3/MemorySearch.fir
@@ -18,7 +18,7 @@ circuit MemorySearch :
     elts[4] := UInt<4>(2)
     elts[5] := UInt<4>(5)
     elts[6] := UInt<4>(13)
-    accessor elt = elts[index]
+    infer accessor elt = elts[index]
     node T_35 = bit-not(en)
     node T_36 = eq(elt, target)
     node T_37 = eq(index, UInt<3>(7))
diff --git a/test/chisel3/Mul.fir b/test/chisel3/Mul.fir
index c5dccb6f..b80b8a83 100644
--- a/test/chisel3/Mul.fir
+++ b/test/chisel3/Mul.fir
@@ -26,5 +26,5 @@ circuit Mul :
     tbl[15] := UInt<4>(9)
     node T_42 = shl(x, 2)
     node T_43 = bit-or(T_42, y)
-    accessor T_44 = tbl[T_43]
+    infer accessor T_44 = tbl[T_43]
     z := T_44
diff --git a/test/chisel3/Risc.fir b/test/chisel3/Risc.fir
index 425f8a91..a1ba01b9 100644
--- a/test/chisel3/Risc.fir
+++ b/test/chisel3/Risc.fir
@@ -14,23 +14,23 @@ circuit Risc :
     cmem code : UInt<32>[256]
     reg pc : UInt<8>
     on-reset pc := UInt<8>(0)
-    accessor inst = code[pc]
+    infer accessor inst = code[pc]
     node op = bits(inst, 31, 24)
     node rci = bits(inst, 23, 16)
     node rai = bits(inst, 15, 8)
     node rbi = bits(inst, 7, 0)
     node T_51 = eq(rai, UInt<1>(0))
-    accessor T_52 = file[rai]
+    infer accessor T_52 = file[rai]
     node ra = mux(T_51, UInt<1>(0), T_52)
     node T_53 = eq(rbi, UInt<1>(0))
-    accessor T_54 = file[rbi]
+    infer accessor T_54 = file[rbi]
     node rb = mux(T_53, UInt<1>(0), T_54)
     wire rc : UInt<32>
     valid := UInt<1>(0)
     out := UInt<1>(0)
     rc := UInt<1>(0)
     when isWr : 
-      accessor T_55 = code[wrAddr]
+      infer accessor T_55 = code[wrAddr]
       T_55 := wrData
     else : when boot : pc := UInt<1>(0)
       else : 
@@ -47,7 +47,7 @@ circuit Risc :
         node T_61 = eq(rci, UInt<8>(255))
         when T_61 : valid := UInt<1>(1)
         else : 
-          accessor T_62 = file[rci]
+          infer accessor T_62 = file[rci]
           T_62 := rc
         node T_63 = add-wrap(pc, UInt<1>(1))
         pc := T_63
diff --git a/test/chisel3/Rom.fir b/test/chisel3/Rom.fir
index 1c19d9b3..f91593a4 100644
--- a/test/chisel3/Rom.fir
+++ b/test/chisel3/Rom.fir
@@ -23,5 +23,5 @@ circuit Rom :
     r[13] := UInt<5>(26)
     r[14] := UInt<5>(28)
     r[15] := UInt<5>(30)
-    accessor T_39 = r[addr]
+    infer accessor T_39 = r[addr]
     out := T_39
diff --git a/test/chisel3/Stack.fir b/test/chisel3/Stack.fir
index caa70da5..52c9b437 100644
--- a/test/chisel3/Stack.fir
+++ b/test/chisel3/Stack.fir
@@ -18,7 +18,7 @@ circuit Stack :
       node T_30 = lt(sp, UInt<5>(16))
       node T_31 = bit-and(push, T_30)
       when T_31 : 
-        accessor T_32 = stack_mem[sp]
+        infer accessor T_32 = stack_mem[sp]
         T_32 := dataIn
         node T_33 = add-wrap(sp, UInt<1>(1))
         sp := T_33
@@ -31,6 +31,6 @@ circuit Stack :
       node T_37 = gt(sp, UInt<1>(0))
       when T_37 : 
         node T_38 = sub-wrap(sp, UInt<1>(1))
-        accessor T_39 = stack_mem[T_38]
+        infer accessor T_39 = stack_mem[T_38]
         out := T_39
     dataOut := out
diff --git a/test/chisel3/Tbl.fir b/test/chisel3/Tbl.fir
index e7397f61..013fd098 100644
--- a/test/chisel3/Tbl.fir
+++ b/test/chisel3/Tbl.fir
@@ -11,9 +11,9 @@ circuit Tbl :
     cmem m : UInt<10>[256]
     o := UInt<1>(0)
     when we : 
-      accessor T_13 = m[i]
+      infer accessor T_13 = m[i]
       node T_14 = bits(d, 9, 0)
       T_13 := T_14
     else : 
-      accessor T_15 = m[i]
+      infer accessor T_15 = m[i]
       o := T_15
diff --git a/test/chisel3/Tile.fir b/test/chisel3/Tile.fir
index b84684db..9efb079c 100644
--- a/test/chisel3/Tile.fir
+++ b/test/chisel3/Tile.fir
@@ -100,19 +100,19 @@ circuit Tile :
     cmem regs : UInt<32>[32]
     node T_1616 = eq(raddr1, UInt<1>(0))
     node T_1617 = bit-not(T_1616)
-    accessor T_1618 = regs[raddr1]
+    infer accessor T_1618 = regs[raddr1]
     node T_1619 = mux(T_1617, T_1618, UInt<1>(0))
     rdata1 := T_1619
     node T_1620 = eq(raddr2, UInt<1>(0))
     node T_1621 = bit-not(T_1620)
-    accessor T_1622 = regs[raddr2]
+    infer accessor T_1622 = regs[raddr2]
     node T_1623 = mux(T_1621, T_1622, UInt<1>(0))
     rdata2 := T_1623
     node T_1624 = eq(waddr, UInt<1>(0))
     node T_1625 = bit-not(T_1624)
     node T_1626 = bit-and(wen, T_1625)
     when T_1626 : 
-      accessor T_1627 = regs[waddr]
+      infer accessor T_1627 = regs[waddr]
       T_1627 := wdata
   module ImmGenWire : 
     output out : UInt<32>
@@ -1046,7 +1046,7 @@ circuit Tile :
     node T_2387 = bit-not(do_flow)
     node do_deq = bit-and(T_2386, T_2387)
     when do_enq : 
-      accessor T_2388 = ram[T_2381]
+      infer accessor T_2388 = ram[T_2381]
       T_2388 := enq.bits
       node T_2389 = eq(T_2381, UInt<2>(3))
       node T_2390 = bit-and(UInt<1>(0), T_2389)
@@ -1069,7 +1069,7 @@ circuit Tile :
     node T_2402 = bit-and(UInt<1>(0), deq.ready)
     node T_2403 = bit-or(T_2401, T_2402)
     enq.ready := T_2403
-    accessor T_2404 = ram[T_2382]
+    infer accessor T_2404 = ram[T_2382]
     wire T_2405 : {mask : UInt<4>, tag : UInt<5>, rw : UInt<1>, addr : UInt<32>}
     node T_2406 = mux(maybe_flow, enq.bits.mask, T_2404.mask)
     T_2405.mask := T_2406
@@ -1109,7 +1109,7 @@ circuit Tile :
     node T_2418 = bit-not(do_flow)
     node do_deq = bit-and(T_2417, T_2418)
     when do_enq : 
-      accessor T_2419 = ram[T_2412]
+      infer accessor T_2419 = ram[T_2412]
       T_2419 := enq.bits
       node T_2420 = eq(T_2412, UInt<2>(3))
       node T_2421 = bit-and(UInt<1>(0), T_2420)
@@ -1132,7 +1132,7 @@ circuit Tile :
     node T_2433 = bit-and(UInt<1>(0), deq.ready)
     node T_2434 = bit-or(T_2432, T_2433)
     enq.ready := T_2434
-    accessor T_2435 = ram[T_2413]
+    infer accessor T_2435 = ram[T_2413]
     wire T_2436 : {data : UInt<32>}
     node T_2437 = mux(maybe_flow, enq.bits.data, T_2435.data)
     T_2436.data := T_2437