diff options
| author | azidar | 2015-06-04 14:56:18 -0700 |
|---|---|---|
| committer | azidar | 2015-06-04 14:56:18 -0700 |
| commit | 06f57fefe8258c7d8149156db7ca01a66f207a5d (patch) | |
| tree | 2598d83574f3675e42e763c18fbb6793b779c8df /test/chisel3/Datapath.fir | |
| parent | d86272ca9238c12e80e78938bc1dd5a1dc8532da (diff) | |
Fixed fir files so they correctly compile to verilog! Front-end needs to generate as-SInt instead of convert, always. Added fast build to Makefile
Diffstat (limited to 'test/chisel3/Datapath.fir')
| -rw-r--r-- | test/chisel3/Datapath.fir | 26 |
1 files changed, 13 insertions, 13 deletions
diff --git a/test/chisel3/Datapath.fir b/test/chisel3/Datapath.fir index c02eeae6..7d684395 100644 --- a/test/chisel3/Datapath.fir +++ b/test/chisel3/Datapath.fir @@ -12,14 +12,14 @@ circuit Datapath : node shamt = bits(B, 4, 0) node T_433 = add-wrap(A, B) node T_434 = sub-wrap(A, B) - node T_435 = convert(A) + node T_435 = as-SInt(A) node T_436 = dshr(T_435, shamt) node T_437 = as-UInt(T_436) node T_438 = dshr(A, shamt) node T_439 = dshl(A, shamt) node T_440 = bits(T_439, 31, 0) - node T_441 = convert(A) - node T_442 = convert(B) + node T_441 = as-SInt(A) + node T_442 = as-SInt(B) node T_443 = lt(T_441, T_442) node T_444 = as-UInt(T_443) node T_445 = lt(A, B) @@ -64,8 +64,8 @@ circuit Datapath : node eq = eq(rs1, rs2) node neq = bit-not(eq) - node T_476 = convert(rs1) - node T_477 = convert(rs2) + node T_476 = as-SInt(rs1) + node T_477 = as-SInt(rs2) node lt = lt(T_476, T_477) node ge = bit-not(lt) node ltu = lt(rs1, rs2) @@ -120,11 +120,11 @@ circuit Datapath : input sel : UInt<3> node T_507 = bits(inst, 31, 20) - node Iimm = convert(T_507) + node Iimm = as-SInt(T_507) node T_508 = bits(inst, 31, 25) node T_509 = bits(inst, 11, 7) node T_510 = cat(T_508, T_509) - node Simm = convert(T_510) + node Simm = as-SInt(T_510) node T_511 = bit(inst, 31) node T_512 = bit(inst, 7) node T_513 = bits(inst, 30, 25) @@ -133,10 +133,10 @@ circuit Datapath : node T_516 = cat(T_514, UInt<1>(0)) node T_517 = cat(T_513, T_516) node T_518 = cat(T_515, T_517) - node Bimm = convert(T_518) + node Bimm = as-SInt(T_518) node T_519 = bits(inst, 31, 12) node T_520 = cat(T_519, UInt<12>(0)) - node Uimm = convert(T_520) + node Uimm = as-SInt(T_520) node T_521 = bit(inst, 31) node T_522 = bits(inst, 19, 12) node T_523 = bit(inst, 20) @@ -147,10 +147,10 @@ circuit Datapath : node T_528 = cat(T_525, UInt<1>(0)) node T_529 = cat(T_524, T_528) node T_530 = cat(T_527, T_529) - node Jimm = convert(T_530) + node Jimm = as-SInt(T_530) node T_531 = bits(inst, 19, 15) node T_532 = pad(T_531, 32) - node Zimm = convert(T_532) + node Zimm = as-SInt(T_532) node T_533 = eq(UInt<3>(3), sel) node T_534 = mux(T_533, Jimm, Zimm) node T_535 = eq(UInt<3>(2), sel) @@ -330,11 +330,11 @@ circuit Datapath : node loffset = bit-or(T_618, T_620) node lshift = dshr(dcache.dout, loffset) node T_621 = bits(lshift, 15, 0) - node T_622 = convert(T_621) + node T_622 = as-SInt(T_621) node T_623 = pad(T_622, 32) node T_624 = as-UInt(T_623) node T_625 = bits(lshift, 7, 0) - node T_626 = convert(T_625) + node T_626 = as-SInt(T_625) node T_627 = pad(T_626, 32) node T_628 = as-UInt(T_627) node T_629 = bits(lshift, 15, 0) |