Fixed fir files so they correctly compile to verilog! Front-end needs to generate as-SInt instead of convert, always. Added fast build to Makefile

6 files changed, 43 insertions, 40 deletions

diff --git a/Makefile b/Makefile
index 9679422e..780c1223 100644
--- a/Makefile
+++ b/Makefile
@@ -20,6 +20,9 @@ build-deploy:
 build: 
 	cd $(firrtl_dir) && stanza -i firrtl-test-main.stanza -o $(root_dir)/utils/bin/firrtl
 
+build-fast: 
+	cd $(firrtl_dir) && stanza -i firrtl-test-main.stanza -o $(root_dir)/utils/bin/firrtl -flags OPTIMIZE
+
 check: 
 	cd $(test_dir) && lit -v . --path=$(root_dir)/utils/bin/
 
diff --git a/src/main/stanza/custom-compiler.stanza b/src/main/stanza/custom-compiler.stanza
index aa21504b..773b63ca 100644
--- a/src/main/stanza/custom-compiler.stanza
+++ b/src/main/stanza/custom-compiler.stanza
@@ -32,7 +32,7 @@ public defmethod passes (c:InstrumentedVerilog) -> List<Pass> :
       SplitExp()
       ToRealIR()
       SpecialRename(`#,`_)
-      CheckHighForm(`_)
+      CheckHighForm(expand-delin)
       CheckLowForm()
       Verilog(file(c))
    ]
diff --git a/src/main/stanza/flo.stanza b/src/main/stanza/flo.stanza
index 22b0c978..fd000e20 100644
--- a/src/main/stanza/flo.stanza
+++ b/src/main/stanza/flo.stanza
@@ -89,7 +89,7 @@ public defn pad-widths (c:Circuit) -> Circuit :
    Circuit{info(c),_,main(c)} $
       for m in modules(c) map :
          match(m) :
-            (m:ExModule) : error("Cannot use flo backend with external modules")
+            (m:ExModule) : m
             (m:InModule) : InModule(info(m),name(m),ports(m),pad-widths-s(body(m)))
 
 ;============= Flo Backend ================
diff --git a/test/chisel3/Core.fir b/test/chisel3/Core.fir
index b2062c1d..5c446b3d 100644
--- a/test/chisel3/Core.fir
+++ b/test/chisel3/Core.fir
@@ -18,8 +18,8 @@ circuit Core :
     node T_1229 = dshr(A, shamt)
     node T_1230 = dshl(A, shamt)
     node T_1231 = bits(T_1230, 31, 0)
-    node T_1232 = convert(A)
-    node T_1233 = convert(B)
+    node T_1232 = as-SInt(A)
+    node T_1233 = as-SInt(B)
     node T_1234 = lt(T_1232, T_1233)
     node T_1235 = as-UInt(T_1234)
     node T_1236 = lt(A, B)
@@ -64,8 +64,8 @@ circuit Core :
     
     node eq = eq(rs1, rs2)
     node neq = bit-not(eq)
-    node T_1267 = convert(rs1)
-    node T_1268 = convert(rs2)
+    node T_1267 = as-SInt(rs1)
+    node T_1268 = as-SInt(rs2)
     node lt = lt(T_1267, T_1268)
     node ge = bit-not(lt)
     node ltu = lt(rs1, rs2)
@@ -120,11 +120,11 @@ circuit Core :
     input inst : UInt<32>
     
     node T_1298 = bits(inst, 31, 20)
-    node Iimm = convert(T_1298)
+    node Iimm = as-SInt(T_1298)
     node T_1299 = bits(inst, 31, 25)
     node T_1300 = bits(inst, 11, 7)
     node T_1301 = cat(T_1299, T_1300)
-    node Simm = convert(T_1301)
+    node Simm = as-SInt(T_1301)
     node T_1302 = bit(inst, 31)
     node T_1303 = bit(inst, 7)
     node T_1304 = bits(inst, 30, 25)
@@ -133,10 +133,10 @@ circuit Core :
     node T_1307 = cat(T_1305, UInt<1>(0))
     node T_1308 = cat(T_1304, T_1307)
     node T_1309 = cat(T_1306, T_1308)
-    node Bimm = convert(T_1309)
+    node Bimm = as-SInt(T_1309)
     node T_1310 = bits(inst, 31, 12)
     node T_1311 = cat(T_1310, UInt<12>(0))
-    node Uimm = convert(T_1311)
+    node Uimm = as-SInt(T_1311)
     node T_1312 = bit(inst, 31)
     node T_1313 = bits(inst, 19, 12)
     node T_1314 = bit(inst, 20)
@@ -147,10 +147,10 @@ circuit Core :
     node T_1319 = cat(T_1316, UInt<1>(0))
     node T_1320 = cat(T_1315, T_1319)
     node T_1321 = cat(T_1318, T_1320)
-    node Jimm = convert(T_1321)
+    node Jimm = as-SInt(T_1321)
     node T_1322 = bits(inst, 19, 15)
     node T_1323 = pad(T_1322, 32)
-    node Zimm = convert(T_1323)
+    node Zimm = as-SInt(T_1323)
     node T_1324 = eq(UInt<3>(3), sel)
     node T_1325 = mux(T_1324, Jimm, Zimm)
     node T_1326 = eq(UInt<3>(2), sel)
@@ -330,11 +330,11 @@ circuit Core :
     node loffset = bit-or(T_1409, T_1411)
     node lshift = dshr(dcache.dout, loffset)
     node T_1412 = bits(lshift, 15, 0)
-    node T_1413 = convert(T_1412)
+    node T_1413 = as-SInt(T_1412)
     node T_1414 = pad(T_1413, 32)
     node T_1415 = as-UInt(T_1414)
     node T_1416 = bits(lshift, 7, 0)
-    node T_1417 = convert(T_1416)
+    node T_1417 = as-SInt(T_1416)
     node T_1418 = pad(T_1417, 32)
     node T_1419 = as-UInt(T_1418)
     node T_1420 = bits(lshift, 15, 0)
diff --git a/test/chisel3/Datapath.fir b/test/chisel3/Datapath.fir
index c02eeae6..7d684395 100644
--- a/test/chisel3/Datapath.fir
+++ b/test/chisel3/Datapath.fir
@@ -12,14 +12,14 @@ circuit Datapath :
     node shamt = bits(B, 4, 0)
     node T_433 = add-wrap(A, B)
     node T_434 = sub-wrap(A, B)
-    node T_435 = convert(A)
+    node T_435 = as-SInt(A)
     node T_436 = dshr(T_435, shamt)
     node T_437 = as-UInt(T_436)
     node T_438 = dshr(A, shamt)
     node T_439 = dshl(A, shamt)
     node T_440 = bits(T_439, 31, 0)
-    node T_441 = convert(A)
-    node T_442 = convert(B)
+    node T_441 = as-SInt(A)
+    node T_442 = as-SInt(B)
     node T_443 = lt(T_441, T_442)
     node T_444 = as-UInt(T_443)
     node T_445 = lt(A, B)
@@ -64,8 +64,8 @@ circuit Datapath :
     
     node eq = eq(rs1, rs2)
     node neq = bit-not(eq)
-    node T_476 = convert(rs1)
-    node T_477 = convert(rs2)
+    node T_476 = as-SInt(rs1)
+    node T_477 = as-SInt(rs2)
     node lt = lt(T_476, T_477)
     node ge = bit-not(lt)
     node ltu = lt(rs1, rs2)
@@ -120,11 +120,11 @@ circuit Datapath :
     input sel : UInt<3>
     
     node T_507 = bits(inst, 31, 20)
-    node Iimm = convert(T_507)
+    node Iimm = as-SInt(T_507)
     node T_508 = bits(inst, 31, 25)
     node T_509 = bits(inst, 11, 7)
     node T_510 = cat(T_508, T_509)
-    node Simm = convert(T_510)
+    node Simm = as-SInt(T_510)
     node T_511 = bit(inst, 31)
     node T_512 = bit(inst, 7)
     node T_513 = bits(inst, 30, 25)
@@ -133,10 +133,10 @@ circuit Datapath :
     node T_516 = cat(T_514, UInt<1>(0))
     node T_517 = cat(T_513, T_516)
     node T_518 = cat(T_515, T_517)
-    node Bimm = convert(T_518)
+    node Bimm = as-SInt(T_518)
     node T_519 = bits(inst, 31, 12)
     node T_520 = cat(T_519, UInt<12>(0))
-    node Uimm = convert(T_520)
+    node Uimm = as-SInt(T_520)
     node T_521 = bit(inst, 31)
     node T_522 = bits(inst, 19, 12)
     node T_523 = bit(inst, 20)
@@ -147,10 +147,10 @@ circuit Datapath :
     node T_528 = cat(T_525, UInt<1>(0))
     node T_529 = cat(T_524, T_528)
     node T_530 = cat(T_527, T_529)
-    node Jimm = convert(T_530)
+    node Jimm = as-SInt(T_530)
     node T_531 = bits(inst, 19, 15)
     node T_532 = pad(T_531, 32)
-    node Zimm = convert(T_532)
+    node Zimm = as-SInt(T_532)
     node T_533 = eq(UInt<3>(3), sel)
     node T_534 = mux(T_533, Jimm, Zimm)
     node T_535 = eq(UInt<3>(2), sel)
@@ -330,11 +330,11 @@ circuit Datapath :
     node loffset = bit-or(T_618, T_620)
     node lshift = dshr(dcache.dout, loffset)
     node T_621 = bits(lshift, 15, 0)
-    node T_622 = convert(T_621)
+    node T_622 = as-SInt(T_621)
     node T_623 = pad(T_622, 32)
     node T_624 = as-UInt(T_623)
     node T_625 = bits(lshift, 7, 0)
-    node T_626 = convert(T_625)
+    node T_626 = as-SInt(T_625)
     node T_627 = pad(T_626, 32)
     node T_628 = as-UInt(T_627)
     node T_629 = bits(lshift, 15, 0)
diff --git a/test/chisel3/Tile.fir b/test/chisel3/Tile.fir
index e85bd56b..b84684db 100644
--- a/test/chisel3/Tile.fir
+++ b/test/chisel3/Tile.fir
@@ -12,14 +12,14 @@ circuit Tile :
     node shamt = bits(B, 4, 0)
     node T_1554 = add-wrap(A, B)
     node T_1555 = sub-wrap(A, B)
-    node T_1556 = convert(A)
+    node T_1556 = as-SInt(A)
     node T_1557 = dshr(T_1556, shamt)
     node T_1558 = as-UInt(T_1557)
     node T_1559 = dshr(A, shamt)
     node T_1560 = dshl(A, shamt)
     node T_1561 = bits(T_1560, 31, 0)
-    node T_1562 = convert(A)
-    node T_1563 = convert(B)
+    node T_1562 = as-SInt(A)
+    node T_1563 = as-SInt(B)
     node T_1564 = lt(T_1562, T_1563)
     node T_1565 = as-UInt(T_1564)
     node T_1566 = lt(A, B)
@@ -64,8 +64,8 @@ circuit Tile :
     
     node eq = eq(rs1, rs2)
     node neq = bit-not(eq)
-    node T_1597 = convert(rs1)
-    node T_1598 = convert(rs2)
+    node T_1597 = as-SInt(rs1)
+    node T_1598 = as-SInt(rs2)
     node lt = lt(T_1597, T_1598)
     node ge = bit-not(lt)
     node ltu = lt(rs1, rs2)
@@ -120,11 +120,11 @@ circuit Tile :
     input sel : UInt<3>
     
     node T_1628 = bits(inst, 31, 20)
-    node Iimm = convert(T_1628)
+    node Iimm = as-SInt(T_1628)
     node T_1629 = bits(inst, 31, 25)
     node T_1630 = bits(inst, 11, 7)
     node T_1631 = cat(T_1629, T_1630)
-    node Simm = convert(T_1631)
+    node Simm = as-SInt(T_1631)
     node T_1632 = bit(inst, 31)
     node T_1633 = bit(inst, 7)
     node T_1634 = bits(inst, 30, 25)
@@ -133,10 +133,10 @@ circuit Tile :
     node T_1637 = cat(T_1635, UInt<1>(0))
     node T_1638 = cat(T_1634, T_1637)
     node T_1639 = cat(T_1636, T_1638)
-    node Bimm = convert(T_1639)
+    node Bimm = as-SInt(T_1639)
     node T_1640 = bits(inst, 31, 12)
     node T_1641 = cat(T_1640, UInt<12>(0))
-    node Uimm = convert(T_1641)
+    node Uimm = as-SInt(T_1641)
     node T_1642 = bit(inst, 31)
     node T_1643 = bits(inst, 19, 12)
     node T_1644 = bit(inst, 20)
@@ -147,10 +147,10 @@ circuit Tile :
     node T_1649 = cat(T_1646, UInt<1>(0))
     node T_1650 = cat(T_1645, T_1649)
     node T_1651 = cat(T_1648, T_1650)
-    node Jimm = convert(T_1651)
+    node Jimm = as-SInt(T_1651)
     node T_1652 = bits(inst, 19, 15)
     node T_1653 = pad(T_1652, 32)
-    node Zimm = convert(T_1653)
+    node Zimm = as-SInt(T_1653)
     node T_1654 = eq(UInt<3>(3), sel)
     node T_1655 = mux(T_1654, Jimm, Zimm)
     node T_1656 = eq(UInt<3>(2), sel)
@@ -330,11 +330,11 @@ circuit Tile :
     node loffset = bit-or(T_1739, T_1741)
     node lshift = dshr(dcache.dout, loffset)
     node T_1742 = bits(lshift, 15, 0)
-    node T_1743 = convert(T_1742)
+    node T_1743 = as-SInt(T_1742)
     node T_1744 = pad(T_1743, 32)
     node T_1745 = as-UInt(T_1744)
     node T_1746 = bits(lshift, 7, 0)
-    node T_1747 = convert(T_1746)
+    node T_1747 = as-SInt(T_1746)
     node T_1748 = pad(T_1747, 32)
     node T_1749 = as-UInt(T_1748)
     node T_1750 = bits(lshift, 15, 0)