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* Correctly handle dots in loaded memory paths
* Added test for loadmem filename
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UniquifySpec.quicklyrenamedeepbundles (#1000)
* Attempt to deal with timing vagaries in UniquifySpec.quicklyrenamedeepbundles
Switching to Scala 2.12.8 cause this test to start failing on OSX. Try earlier scheme to compare shallow vs deep to reduce brittleness.
* Address review concerns; update comment.
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Fixes #219
* Adds AsyncResetType (similar to ClockType)
* Registers with reset signal of type AsyncResetType are async reset
registers
* Registers with async reset can only be reset to literal values
* Add initialization logic for async reset registers
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This uses the foldShiftRight method of the ConstantPropagation
Transform when legalizing Shr PrimOps. This has the effect of removing
literals with bit extracts from the MinimumVerilogCompiler.
This makes the formerly private foldShiftRight method of a public
method of the ConstantPropagation companion object.
Tests in the MimimumVerilogCompilerSpec are updated to check that Shr
is handled as intended.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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This adds the RemoveValidIf Pass to the MinimumLowFirrtlOptimization
Transform. A test case is included to verify that `is invalid` is
properly converted to a connection to zero.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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This adds runs of the minimum Verilog compiler and SystemVerilog
compiler in DriverSpec.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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This adds "mverilog" to the "--compiler" command line option. This
will run the MinimumVerilogCompiler.
This additionally fixes the MinimumVerilogCompiler such that
DeadCodeElimination will not be run (it's not supposed to be). This is
done by adding a MinimumVerilogEmitter, subclassing VerilogVerilog,
that strips the DeadCodeElimination step from its parent.
Additionally, BlackBoxSourceHelper is removed from the
MinimumVerilogCompiler since this will be run by the VerilogEmitter
already.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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* Enhance constant propagation across registers
* Add more elaborate test case for register const prop
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* Add memory WRef factory for completeness
* Refactor DefAnnotatedMemory construction for clarity
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make more clear for ExecutionOptionsManager log level settings.
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* Improve Shl codegen; eliminate Shlw WIR node
If we emit shl(x, k) as {x, k'h0} instead of (x << k), then there's
no need for Verilog-specific padding in the PadWidths pass. Avoiding
the redundant padding improves compiler/simulator performance and
renders Shlw unnecessary.
* [skip formal checks] Add test
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Fixes #990
h/t @pentin-as and @abejgonzalez
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This fixes issue #988
I tried one alternative to this fix: record the time to do a *no rename* run (`depth = 0`) and check that the time to do the *deep rename* (`depth = 500`) was a reasonable multiple of the *no rename* test. Unfortunately, the discrepancies were all over the map, sometime as much three orders of magnitude difference.
I decided the current fix was the simplest - don't enforce timing checks if we're doing coverage testing, although determining the latter is brittle.
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Previously, components that did not affect the output would cause
exceptions because they were missing from the label2group Map. This
commit treats them as "reachable" by the ports so they are included in
the default "ungrouped" group.
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This fixes an issue where expressions created by GroupComponents would
be improperly lowered because they were not marked as references to
instance ports.
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* Seal Direction trait
* Add WRef factories for ports and instances
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This adds a requirement that all Compilers must have at least one
Transform. Without this, there is no way to determine the inputForm or
outputForm of a given compiler as these are (rightly) defined in terms of
the head/last transform.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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This changes the NoneCompiler to be a unary sequence consisting of an
IdentityTransform. This fixes the inputForm and outputForm inherited
methods that implicitly mandate a non-empty transform sequence.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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This adds an identity transform that applies an identity function to some
CircuitState, i.e., it just returns the original CircuitState. This is
useful for transform generators that may, for edge cases, generate an
empty transform sequence. Other classes (e.g., Compiler) have explicit or
implicit requirements that a transform sequence is non-empty.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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* Give better error when mport references non-existent memory
* Closes #796
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This fixes a bug where DiGraph summation (using the `+` operator) would
mutate the DiGraph. This occurred because the underlying edges set was not
being cloned. This is fixed to explicitly clone the underlying edges set.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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Iterating on a HashSet could cause identical modules (including
annotations) to not dedup
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* Added Foreachers
* Changed CheckTypes to use foreach
* Check widths now uses foreach
* Finished merge, added foreachers to added stmts
* Address reviewer feedback
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Where the high form compiler removes Chirrtl (and runs some checks),
this compiler does nothing but read in the circuit and then emit it
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This breaks firrtl.options.Stage into a small type hierarchy:
* Phase: something that transforms an AnnotationSeq
* Stage extends Phase: a Phase with a Command Line Interface
Some of the old "common options" (input annotation file and target
directory) are moved into firrtl.options and provided as part of the Stage
class. Stage will automatically preprocess an input annotation sequence to
resolve all input annotation files and add a default target directory.
Minor changes:
* Adds ViewException
* Stops mixing in the DoNotTerminateOnExit trait into the default Shell
parser
* Add StageOptionsView
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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Signed-off-by: Schuyler Eldridge <schuyler.eldridge@gmail.com>
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Huge performance improvement when you have lots of ports for a given
module. Also split up some long implicit argument lines.
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- Add firrtl.transforms.CombineCats
- Use CombineCats in LowFirrtlOptimization
- Modify Verilog emitter to allow for nested Cat DoPrims
- Modify firrtlEquivalenceTest to write input FIRRTL string to test directory
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TargetDirAnnotation was moved from firrtl to firrtl.stage. However, this
is only aliased as a val in the firrtl package object. This also needs to
be type aliased for matching against a type. This fixes a bug I ran across
in the visualizer.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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This shows an example of using a RegisteredLibrary, with the appropriate
META-INF ServiceLoader entry, that adds options from the InferReadWrite
and ReplSeqMem transforms.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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