diff options
| author | Schuyler Eldridge | 2018-08-22 16:08:00 -0400 |
|---|---|---|
| committer | Schuyler Eldridge | 2018-11-07 13:49:16 -0500 |
| commit | b05eaea3e59c64d619a544c63311d510f335f7e5 (patch) | |
| tree | 7ae4e04a16eb87ce306a9d891acabbd4c6b1c8b7 /src | |
| parent | f5a0c8040cac6567f47f5bd64ae5c3c36403148b (diff) | |
Make ClockListAnnotation a RegisteredTransform
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/main/resources/META-INF/services/firrtl.options.RegisteredTransform | 1 | ||||
| -rw-r--r-- | src/main/scala/firrtl/passes/clocklist/ClockListTransform.scala | 12 |
2 files changed, 12 insertions, 1 deletions
diff --git a/src/main/resources/META-INF/services/firrtl.options.RegisteredTransform b/src/main/resources/META-INF/services/firrtl.options.RegisteredTransform index 3ba17c46..638404be 100644 --- a/src/main/resources/META-INF/services/firrtl.options.RegisteredTransform +++ b/src/main/resources/META-INF/services/firrtl.options.RegisteredTransform @@ -1,3 +1,4 @@ firrtl.transforms.DeadCodeElimination firrtl.transforms.CheckCombLoops firrtl.passes.InlineInstances +firrtl.passes.clocklist.ClockListTransform diff --git a/src/main/scala/firrtl/passes/clocklist/ClockListTransform.scala b/src/main/scala/firrtl/passes/clocklist/ClockListTransform.scala index 6b265239..8d70f211 100644 --- a/src/main/scala/firrtl/passes/clocklist/ClockListTransform.scala +++ b/src/main/scala/firrtl/passes/clocklist/ClockListTransform.scala @@ -57,9 +57,19 @@ Usage: } } -class ClockListTransform extends Transform { +class ClockListTransform extends Transform with RegisteredTransform { def inputForm = LowForm def outputForm = LowForm + + def addOptions(parser: OptionParser[AnnotationSeq]): Unit = parser + .opt[String]("list-clocks") + .abbr("clks") + .valueName ("-c:<circuit>:-m:<module>:-o:<filename>") + .action( (x, c) => c ++ Seq(passes.clocklist.ClockListAnnotation.parse(x), + RunFirrtlTransformAnnotation(new ClockListTransform)) ) + .maxOccurs(1) + .text("List which signal drives each clock of every descendent of specified module") + def passSeq(top: String, writer: Writer): Seq[Pass] = Seq(new ClockList(top, writer)) def execute(state: CircuitState): CircuitState = { |