Add "mverilog" Compiler Option, Compiler Fixes

This adds "mverilog" to the "--compiler" command line option. This
will run the MinimumVerilogCompiler.

This additionally fixes the MinimumVerilogCompiler such that
DeadCodeElimination will not be run (it's not supposed to be). This is
done by adding a MinimumVerilogEmitter, subclassing VerilogVerilog,
that strips the DeadCodeElimination step from its parent.

Additionally, BlackBoxSourceHelper is removed from the
MinimumVerilogCompiler since this will be run by the VerilogEmitter
already.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

4 files changed, 57 insertions, 12 deletions

diff --git a/src/main/scala/firrtl/Emitter.scala b/src/main/scala/firrtl/Emitter.scala
index 67bd1583..8049e33c 100644
--- a/src/main/scala/firrtl/Emitter.scala
+++ b/src/main/scala/firrtl/Emitter.scala
@@ -882,3 +882,13 @@ class VerilogEmitter extends SeqTransform with Emitter {
     state.copy(annotations = newAnnos ++ state.annotations)
   }
 }
+
+class MinimumVerilogEmitter extends VerilogEmitter with Emitter {
+
+
+  override def transforms = super.transforms.filter{
+    case _: DeadCodeElimination => false
+    case _ => true
+  }
+
+}
diff --git a/src/main/scala/firrtl/ExecutionOptionsManager.scala b/src/main/scala/firrtl/ExecutionOptionsManager.scala
index 16e30f3a..47083cb4 100644
--- a/src/main/scala/firrtl/ExecutionOptionsManager.scala
+++ b/src/main/scala/firrtl/ExecutionOptionsManager.scala
@@ -207,18 +207,19 @@ extends ComposableOptions {
       case "low"       => new LowFirrtlCompiler()
       case "middle"    => new MiddleFirrtlCompiler()
       case "verilog"   => new VerilogCompiler()
+      case "mverilog"  => new MinimumVerilogCompiler()
       case "sverilog"  => new SystemVerilogCompiler()
     }
   }
 
   def outputSuffix: String = {
     compilerName match {
-      case "verilog"   => "v"
-      case "sverilog"  => "sv"
-      case "low"       => "lo.fir"
-      case "middle"    => "mid.fir"
-      case "high"      => "hi.fir"
-      case "none"      => "fir"
+      case "verilog" | "mverilog" => "v"
+      case "sverilog"             => "sv"
+      case "low"                  => "lo.fir"
+      case "middle"               => "mid.fir"
+      case "high"                 => "hi.fir"
+      case "none"                 => "fir"
       case _ =>
         throw new Exception(s"Illegal compiler name $compilerName")
     }
@@ -267,6 +268,7 @@ extends ComposableOptions {
       case "middle" => classOf[MiddleFirrtlEmitter]
       case "low" => classOf[LowFirrtlEmitter]
       case "verilog" => classOf[VerilogEmitter]
+      case "mverilog" => classOf[MinimumVerilogEmitter]
       case "sverilog" => classOf[VerilogEmitter]
     }
     getOutputConfig(optionsManager) match {
@@ -344,13 +346,16 @@ trait HasFirrtlOptions {
 
   parser.opt[String]("compiler")
     .abbr("X")
-    .valueName ("<high|middle|low|verilog|sverilog|none>")
+    .valueName ("<high|middle|low|verilog|mverilog|sverilog|none>")
     .foreach { x =>
       firrtlOptions = firrtlOptions.copy(compilerName = x)
     }
     .validate { x =>
-      if (Array("high", "middle", "low", "verilog", "sverilog", "none").contains(x.toLowerCase)) parser.success
-      else parser.failure(s"$x not a legal compiler")
+      if (Array("high", "middle", "low", "verilog", "mverilog", "sverilog", "none").contains(x.toLowerCase)) {
+        parser.success
+      } else {
+        parser.failure(s"$x not a legal compiler")
+      }
     }.text {
       s"compiler to use, default is ${firrtlOptions.compilerName}"
     }
@@ -492,7 +497,8 @@ object FirrtlExecutionSuccess {
   * Indicates a successful execution of the firrtl compiler, returning the compiled result and
   * the type of compile
   *
-  * @param emitType  The name of the compiler used, currently "high", "middle", "low", "verilog", or "sverilog"
+  * @param emitType The name of the compiler used, currently "high", "middle", "low", "verilog", "mverilog", or
+  * "sverilog"
   * @param emitted   The emitted result of compilation
   */
 class FirrtlExecutionSuccess(
diff --git a/src/main/scala/firrtl/LoweringCompilers.scala b/src/main/scala/firrtl/LoweringCompilers.scala
index eab928c2..7499d6d1 100644
--- a/src/main/scala/firrtl/LoweringCompilers.scala
+++ b/src/main/scala/firrtl/LoweringCompilers.scala
@@ -166,9 +166,9 @@ class VerilogCompiler extends Compiler {
 
 /** Emits Verilog without optimizations */
 class MinimumVerilogCompiler extends Compiler {
-  def emitter = new VerilogEmitter
+  def emitter = new MinimumVerilogEmitter
   def transforms: Seq[Transform] = getLoweringTransforms(ChirrtlForm, LowForm) ++
-    Seq(new MinimumLowFirrtlOptimization, new BlackBoxSourceHelper)
+    Seq(new MinimumLowFirrtlOptimization)
 }
 
 /** Currently just an alias for the [[VerilogCompiler]] */
diff --git a/src/test/scala/firrtlTests/CompilerTests.scala b/src/test/scala/firrtlTests/CompilerTests.scala
index 348ed300..ff7d2cb8 100644
--- a/src/test/scala/firrtlTests/CompilerTests.scala
+++ b/src/test/scala/firrtlTests/CompilerTests.scala
@@ -13,6 +13,7 @@ import firrtl.{
   Compiler,
   HighFirrtlCompiler,
   MiddleFirrtlCompiler,
+  MinimumVerilogCompiler,
   LowFirrtlCompiler,
   Parser,
   VerilogCompiler
@@ -153,3 +154,31 @@ class VerilogCompilerSpec extends CompilerSpec with Matchers {
       getOutput should be (check)
    }
 }
+
+class MinimumVerilogCompilerSpec extends CompilerSpec with Matchers {
+  val input = """|circuit Top:
+                 |  module Top:
+                 |    output b: UInt<1>[2]
+                 |    node c = UInt<1>("h0")
+                 |    node d = UInt<1>("h0")
+                 |    b[0] <= UInt<1>("h0")
+                 |    b[1] <= c
+                 |""".stripMargin
+  val check = """|module Top(
+                 |  output  b_0,
+                 |  output  b_1
+                 |);
+                 |  wire  c;
+                 |  wire  d;
+                 |  assign c = 1'h0;
+                 |  assign d = 1'h0;
+                 |  assign b_0 = 1'h0;
+                 |  assign b_1 = c;
+                 |endmodule
+                 |""".stripMargin
+  def compiler = new MinimumVerilogCompiler()
+
+  "A circuit's minimum Verilog output" should "not have constants propagated or dead code eliminated" in {
+    getOutput should be (check)
+  }
+}