Replace Mappers with Foreachers in several passes (#954)

16 files changed, 90 insertions, 131 deletions

diff --git a/src/main/scala/firrtl/Emitter.scala b/src/main/scala/firrtl/Emitter.scala
index 7be049ed..8547f9b9 100644
--- a/src/main/scala/firrtl/Emitter.scala
+++ b/src/main/scala/firrtl/Emitter.scala
@@ -14,7 +14,7 @@ import firrtl.ir._
 import firrtl.passes._
 import firrtl.transforms._
 import firrtl.annotations._
-import firrtl.Mappers._
+import firrtl.traversals.Foreachers._
 import firrtl.PrimOps._
 import firrtl.WrappedExpression._
 import Utils._
@@ -69,15 +69,11 @@ sealed abstract class FirrtlEmitter(form: CircuitForm) extends Transform with Em
     def collectInstantiatedModules(mod: Module, map: Map[String, DefModule]): Seq[DefModule] = {
       // Use list instead of set to maintain order
       val modules = mutable.ArrayBuffer.empty[DefModule]
-      def onStmt(stmt: Statement): Statement = stmt match {
-        case DefInstance(_, _, name) =>
-          modules += map(name)
-          stmt
-        case WDefInstance(_, _, name, _) =>
-          modules += map(name)
-          stmt
+      def onStmt(stmt: Statement): Unit = stmt match {
+        case DefInstance(_, _, name) => modules += map(name)
+        case WDefInstance(_, _, name, _) => modules += map(name)
         case _: WDefInstanceConnector => throwInternalError(s"unrecognized statement: $stmt")
-        case other => other map onStmt
+        case other => other.foreach(onStmt)
       }
       onStmt(mod.body)
       modules.distinct
@@ -399,16 +395,16 @@ class VerilogEmitter extends SeqTransform with Emitter {
     val netlist = mutable.LinkedHashMap[WrappedExpression, Expression]()
     val namespace = Namespace(m)
     namespace.newName("_RAND") // Start rand names at _RAND_0
-    def build_netlist(s: Statement): Statement = s map build_netlist match {
-      case sx: Connect =>
-        netlist(sx.loc) = sx.expr
-        sx
-      case sx: IsInvalid => error("Should have removed these!")
-      case sx: DefNode =>
-        val e = WRef(sx.name, sx.value.tpe, NodeKind, MALE)
-        netlist(e) = sx.value
-        sx
-      case sx => sx
+    def build_netlist(s: Statement): Unit = {
+      s.foreach(build_netlist)
+      s match {
+        case sx: Connect => netlist(sx.loc) = sx.expr
+        case sx: IsInvalid => error("Should have removed these!")
+        case sx: DefNode =>
+          val e = WRef(sx.name, sx.value.tpe, NodeKind, MALE)
+          netlist(e) = sx.value
+        case _ =>
+      }
     }
 
     val portdefs = ArrayBuffer[Seq[Any]]()
@@ -597,7 +593,7 @@ class VerilogEmitter extends SeqTransform with Emitter {
       }
     }
 
-    def build_streams(s: Statement): Statement = {
+    def build_streams(s: Statement): Unit = {
       val withoutDescription = s match {
         case DescribedStmt(DocString(desc), stmt) =>
           val comment = Seq("") +: build_comment(desc.string)
@@ -610,29 +606,24 @@ class VerilogEmitter extends SeqTransform with Emitter {
         case DescribedStmt(EmptyDescription, stmt) => stmt
         case other => other
       }
-      withoutDescription map build_streams match {
+      withoutDescription.foreach(build_streams)
+      withoutDescription match {
         case sx@Connect(info, loc@WRef(_, _, PortKind | WireKind | InstanceKind, _), expr) =>
           assign(loc, expr, info)
-          sx
         case sx: DefWire =>
           declare("wire", sx.name, sx.tpe, sx.info)
-          sx
         case sx: DefRegister =>
           declare("reg", sx.name, sx.tpe, sx.info)
           val e = wref(sx.name, sx.tpe)
           regUpdate(e, sx.clock)
           initialize(e)
-          sx
         case sx: DefNode =>
           declare("wire", sx.name, sx.value.tpe, sx.info)
           assign(WRef(sx.name, sx.value.tpe, NodeKind, MALE), sx.value, sx.info)
-          sx
         case sx: Stop =>
           simulate(sx.clk, sx.en, stop(sx.ret), Some("STOP_COND"), sx.info)
-          sx
         case sx: Print =>
           simulate(sx.clk, sx.en, printf(sx.string, sx.args), Some("PRINTF_COND"), sx.info)
-          sx
         // If we are emitting an Attach, it must not have been removable in VerilogPrep
         case sx: Attach =>
           // For Synthesis
@@ -647,7 +638,6 @@ class VerilogEmitter extends SeqTransform with Emitter {
           }
           // alias implementation for everything else
           attachAliases += Seq("alias ", sx.exprs.flatMap(e => Seq(e, " = ")).init, ";", sx.info)
-          sx
         case sx: WDefInstanceConnector =>
           val (module, params) = moduleMap(sx.module) match {
             case DescribedMod(_, _, ExtModule(_, _, _, extname, params)) => (extname, params)
@@ -663,7 +653,6 @@ class VerilogEmitter extends SeqTransform with Emitter {
             else instdeclares += line
           }
           instdeclares += Seq(");")
-          sx
         case sx: DefMemory =>
           val fullSize = sx.depth * (sx.dataType match {
             case GroundType(IntWidth(width)) => width
@@ -727,8 +716,7 @@ class VerilogEmitter extends SeqTransform with Emitter {
           if (sx.readwriters.nonEmpty)
             throw EmitterException("All readwrite ports should be transformed into " +
               "read & write ports by previous passes")
-          sx
-        case sx => sx
+        case _ =>
       }
     }
 
diff --git a/src/main/scala/firrtl/Namespace.scala b/src/main/scala/firrtl/Namespace.scala
index cc5d8967..11595ba3 100644
--- a/src/main/scala/firrtl/Namespace.scala
+++ b/src/main/scala/firrtl/Namespace.scala
@@ -5,7 +5,6 @@ package firrtl
 import scala.collection.mutable
 import scala.collection.mutable.HashSet
 import firrtl.ir._
-import Mappers._
 
 class Namespace private {
   private val tempNamePrefix: String = "_GEN"
diff --git a/src/main/scala/firrtl/analyses/InstanceGraph.scala b/src/main/scala/firrtl/analyses/InstanceGraph.scala
index 00689a51..c4a70c73 100644
--- a/src/main/scala/firrtl/analyses/InstanceGraph.scala
+++ b/src/main/scala/firrtl/analyses/InstanceGraph.scala
@@ -7,7 +7,7 @@ import firrtl._
 import firrtl.ir._
 import firrtl.graph._
 import firrtl.Utils._
-import firrtl.Mappers._
+import firrtl.traversals.Foreachers._
 import firrtl.annotations.TargetToken.{Instance, OfModule}
 
 
@@ -24,7 +24,7 @@ class InstanceGraph(c: Circuit) {
     new mutable.LinkedHashMap[String, mutable.LinkedHashSet[WDefInstance]]
   for (m <- c.modules) {
     childInstances(m.name) = new mutable.LinkedHashSet[WDefInstance]
-    m map InstanceGraph.collectInstances(childInstances(m.name))
+    m.foreach(InstanceGraph.collectInstances(childInstances(m.name)))
     instantiated ++= childInstances(m.name).map(i => i.module)
   }
 
@@ -117,12 +117,10 @@ object InstanceGraph {
     * @return
     */
   def collectInstances(insts: mutable.Set[WDefInstance])
-                      (s: Statement): Statement = s match {
-    case i: WDefInstance =>
-      insts += i
-      i
+                      (s: Statement): Unit = s match {
+    case i: WDefInstance => insts += i
     case i: DefInstance => throwInternalError("Expecting WDefInstance, found a DefInstance!")
     case i: WDefInstanceConnector => throwInternalError("Expecting WDefInstance, found a WDefInstanceConnector!")
-    case _ => s map collectInstances(insts)
+    case _ => s.foreach(collectInstances(insts))
   }
 }
diff --git a/src/main/scala/firrtl/passes/CheckChirrtl.scala b/src/main/scala/firrtl/passes/CheckChirrtl.scala
index 8f37c8bf..a9a14982 100644
--- a/src/main/scala/firrtl/passes/CheckChirrtl.scala
+++ b/src/main/scala/firrtl/passes/CheckChirrtl.scala
@@ -5,7 +5,7 @@ package firrtl.passes
 import firrtl._
 import firrtl.ir._
 import firrtl.Utils._
-import firrtl.Mappers._
+import firrtl.traversals.Foreachers._
 
 object CheckChirrtl extends Pass {
   type NameSet = collection.mutable.HashSet[String]
@@ -40,54 +40,51 @@ object CheckChirrtl extends Pass {
         errors append new InvalidLOCException(info, mname)
       case _ => // Do Nothing
     }
-    def checkChirrtlW(info: Info, mname: String)(w: Width): Width = w match {
-      case w: IntWidth if (w.width < BigInt(0)) =>
-        errors.append(new NegWidthException(info, mname))
-        w
-      case _ => w
+    def checkChirrtlW(info: Info, mname: String)(w: Width): Unit = w match {
+      case w: IntWidth if (w.width < BigInt(0)) => errors.append(new NegWidthException(info, mname))
+      case _ =>
     }
 
-    def checkChirrtlT(info: Info, mname: String)(t: Type): Type =
-      t map checkChirrtlT(info, mname) match {
+    def checkChirrtlT(info: Info, mname: String)(t: Type): Unit = {
+      t.foreach(checkChirrtlT(info, mname))
+      t match {
         case t: VectorType if t.size < 0 =>
           errors append new NegVecSizeException(info, mname)
-          t map checkChirrtlW(info, mname)
+          t.foreach(checkChirrtlW(info, mname))
         //case FixedType(width, point) => FixedType(checkChirrtlW(width), point)
-        case _ => t map checkChirrtlW(info, mname)
+        case _ => t.foreach(checkChirrtlW(info, mname))
       }
+    }
 
-    def validSubexp(info: Info, mname: String)(e: Expression): Expression = {
-      e match {
-        case _: Reference | _: SubField | _: SubIndex | _: SubAccess |
-             _: Mux | _: ValidIf => // No error
-        case _ => errors append new InvalidAccessException(info, mname)
-      }
-      e
+    def validSubexp(info: Info, mname: String)(e: Expression): Unit = e match {
+      case _: Reference | _: SubField | _: SubIndex | _: SubAccess |
+           _: Mux | _: ValidIf => // No error
+      case _ => errors append new InvalidAccessException(info, mname)
     }
 
-    def checkChirrtlE(info: Info, mname: String, names: NameSet)(e: Expression): Expression = {
+    def checkChirrtlE(info: Info, mname: String, names: NameSet)(e: Expression): Unit = {
       e match {
         case _: DoPrim | _:Mux | _:ValidIf | _: UIntLiteral =>
         case ex: Reference if !names(ex.name) =>
           errors append new UndeclaredReferenceException(info, mname, ex.name)
         case ex: SubAccess => validSubexp(info, mname)(ex.expr)
-        case ex => ex map validSubexp(info, mname)
+        case ex => ex.foreach(validSubexp(info, mname))
       }
-      (e map checkChirrtlW(info, mname)
-         map checkChirrtlT(info, mname)
-         map checkChirrtlE(info, mname, names))
+      e.foreach(checkChirrtlW(info, mname))
+      e.foreach(checkChirrtlT(info, mname))
+      e.foreach(checkChirrtlE(info, mname, names))
     }
 
-    def checkName(info: Info, mname: String, names: NameSet)(name: String): String = {
+    def checkName(info: Info, mname: String, names: NameSet)(name: String): Unit = {
       if (names(name))
         errors append new NotUniqueException(info, mname, name)
       names += name
-      name 
     }
 
-    def checkChirrtlS(minfo: Info, mname: String, names: NameSet)(s: Statement): Statement = {
+    def checkChirrtlS(minfo: Info, mname: String, names: NameSet)(s: Statement): Unit = {
       val info = get_info(s) match {case NoInfo => minfo case x => x}
-      s map checkName(info, mname, names) match {
+      s.foreach(checkName(info, mname, names))
+      s match {
         case sx: DefMemory =>
           if (hasFlip(sx.dataType)) errors append new MemWithFlipException(info, mname, sx.name)
           if (sx.depth <= 0) errors append new NegMemSizeException(info, mname)
@@ -97,27 +94,26 @@ object CheckChirrtl extends Pass {
         case sx: PartialConnect => checkValidLoc(info, mname, sx.loc)
         case _ => // Do Nothing
       }
-      (s map checkChirrtlT(info, mname)
-         map checkChirrtlE(info, mname, names)
-         map checkChirrtlS(info, mname, names))
+      s.foreach(checkChirrtlT(info, mname))
+      s.foreach(checkChirrtlE(info, mname, names))
+      s.foreach(checkChirrtlS(info, mname, names))
     }
 
-    def checkChirrtlP(mname: String, names: NameSet)(p: Port): Port = {
+    def checkChirrtlP(mname: String, names: NameSet)(p: Port): Unit = {
       if (names(p.name))
         errors append new NotUniqueException(NoInfo, mname, p.name)
       names += p.name
-      (p.tpe map checkChirrtlT(p.info, mname)
-             map checkChirrtlW(p.info, mname))
-      p
+      p.tpe.foreach(checkChirrtlT(p.info, mname))
+      p.tpe.foreach(checkChirrtlW(p.info, mname))
     }
 
     def checkChirrtlM(m: DefModule) {
       val names = new NameSet
-      (m map checkChirrtlP(m.name, names)
-         map checkChirrtlS(m.info, m.name, names))
+      m.foreach(checkChirrtlP(m.name, names))
+      m.foreach(checkChirrtlS(m.info, m.name, names))
     }
     
-    c.modules foreach checkChirrtlM
+    c.modules.foreach(checkChirrtlM)
     c.modules count (_.name == c.main) match {
       case 1 =>
       case _ => errors append new NoTopModuleException(c.info, c.main)
diff --git a/src/main/scala/firrtl/passes/CheckInitialization.scala b/src/main/scala/firrtl/passes/CheckInitialization.scala
index 4c392510..d1b6a03f 100644
--- a/src/main/scala/firrtl/passes/CheckInitialization.scala
+++ b/src/main/scala/firrtl/passes/CheckInitialization.scala
@@ -5,7 +5,7 @@ package firrtl.passes
 import firrtl._
 import firrtl.ir._
 import firrtl.Utils._
-import firrtl.Mappers._
+import firrtl.traversals.Foreachers._
 
 import annotation.tailrec
 
@@ -41,35 +41,31 @@ object CheckInitialization extends Pass {
       def hasVoidExpr(e: Expression): (Boolean, Seq[Expression]) = {
         var void = false
         val voidDeps = collection.mutable.ArrayBuffer[Expression]()
-        def hasVoid(e: Expression): Expression = e match {
+        def hasVoid(e: Expression): Unit = e match {
           case WVoid =>
             void = true
-            e
           case (_: WRef | _: WSubField) =>
             if (voidExprs.contains(e)) {
               void = true
               voidDeps += e
             }
-            e
-          case _ => e map hasVoid
+          case _ => e.foreach(hasVoid)
         }
         hasVoid(e)
         (void, voidDeps)
       }
-      def checkInitS(s: Statement): Statement = {
+      def checkInitS(s: Statement): Unit = {
         s match {
           case con: Connect =>
             val (hasVoid, voidDeps) = hasVoidExpr(con.expr)
             if (hasVoid) voidExprs(con.loc) = VoidExpr(con, voidDeps)
-            con
           case node: DefNode =>
             val (hasVoid, voidDeps) = hasVoidExpr(node.value)
             if (hasVoid) {
               val nodeRef = WRef(node.name, node.value.tpe, NodeKind, MALE)
               voidExprs(nodeRef) = VoidExpr(node, voidDeps)
             }
-            node
-          case sx => sx map checkInitS
+          case sx => sx.foreach(checkInitS)
         }
       }
       checkInitS(m.body)
@@ -85,7 +81,7 @@ object CheckInitialization extends Pass {
       }
     }
 
-    c.modules foreach {
+    c.modules.foreach {
       case m: Module => checkInitM(m)
       case m => // Do nothing
     }
diff --git a/src/main/scala/firrtl/passes/Checks.scala b/src/main/scala/firrtl/passes/Checks.scala
index bc9d3a1c..4b996f5d 100644
--- a/src/main/scala/firrtl/passes/Checks.scala
+++ b/src/main/scala/firrtl/passes/Checks.scala
@@ -6,7 +6,6 @@ import firrtl._
 import firrtl.ir._
 import firrtl.PrimOps._
 import firrtl.Utils._
-import firrtl.Mappers._
 import firrtl.traversals.Foreachers._
 import firrtl.WrappedType._
 
@@ -539,7 +538,7 @@ object CheckGenders extends Pass {
           check_gender(info, mname, genders, FEMALE)(s.loc)
           check_gender(info, mname, genders, MALE)(s.expr)
         case (s: Print) =>
-          s.args map check_gender(info, mname, genders, MALE)
+          s.args foreach check_gender(info, mname, genders, MALE)
           check_gender(info, mname, genders, MALE)(s.en)
           check_gender(info, mname, genders, MALE)(s.clk)
         case (s: PartialConnect) =>
diff --git a/src/main/scala/firrtl/passes/InferWidths.scala b/src/main/scala/firrtl/passes/InferWidths.scala
index 26d346bb..6420c3a2 100644
--- a/src/main/scala/firrtl/passes/InferWidths.scala
+++ b/src/main/scala/firrtl/passes/InferWidths.scala
@@ -10,6 +10,7 @@ import firrtl._
 import firrtl.ir._
 import firrtl.Utils._
 import firrtl.Mappers._
+import firrtl.traversals.Foreachers._
 
 object InferWidths extends Pass {
   type ConstraintMap = collection.mutable.LinkedHashMap[String, Width]
@@ -239,7 +240,7 @@ object InferWidths extends Pass {
       case (t1: VectorType, t2: VectorType) => get_constraints_t(t1.tpe, t2.tpe)
     }
 
-    def get_constraints_e(e: Expression): Expression = {
+    def get_constraints_e(e: Expression): Unit = {
       e match {
         case (e: Mux) => v ++= Seq(
           WGeq(getWidth(e.cond), IntWidth(1)),
@@ -247,7 +248,7 @@ object InferWidths extends Pass {
         )
         case _ =>
       }
-      e map get_constraints_e
+      e.foreach(get_constraints_e)
     }
 
     def get_constraints_declared_type (t: Type): Type = t match {
@@ -257,7 +258,7 @@ object InferWidths extends Pass {
       case _ => t map get_constraints_declared_type
     }
 
-    def get_constraints_s(s: Statement): Statement = {
+    def get_constraints_s(s: Statement): Unit = {
       s map get_constraints_declared_type match {
         case (s: Connect) =>
           val n = get_size(s.loc.tpe)
@@ -294,11 +295,12 @@ object InferWidths extends Pass {
           v ++= widths.tail map (WGeq(widths.head, _))
         case _ =>
       }
-      s map get_constraints_e map get_constraints_s
+      s.foreach(get_constraints_e)
+      s.foreach(get_constraints_s)
     }
 
-    c.modules foreach (_ map get_constraints_s)
-    c.modules foreach (_.ports foreach {p => get_constraints_declared_type(p.tpe)})
+    c.modules.foreach(_.foreach(get_constraints_s))
+    c.modules.foreach(_.ports.foreach({p => get_constraints_declared_type(p.tpe)}))
 
     //println("======== ALL CONSTRAINTS ========")
     //for(x <- v) println(x)
diff --git a/src/main/scala/firrtl/passes/clocklist/ClockList.scala b/src/main/scala/firrtl/passes/clocklist/ClockList.scala
index 7be43471..984fd813 100644
--- a/src/main/scala/firrtl/passes/clocklist/ClockList.scala
+++ b/src/main/scala/firrtl/passes/clocklist/ClockList.scala
@@ -14,7 +14,6 @@ import ClockListUtils._
 import Utils._
 import memlib.AnalysisUtils._
 import memlib._
-import Mappers._
 
 /** Starting with a top module, determine the clock origins of each child instance.
  *  Write the result to writer.
diff --git a/src/main/scala/firrtl/passes/clocklist/ClockListTransform.scala b/src/main/scala/firrtl/passes/clocklist/ClockListTransform.scala
index 8d70f211..de9f6c52 100644
--- a/src/main/scala/firrtl/passes/clocklist/ClockListTransform.scala
+++ b/src/main/scala/firrtl/passes/clocklist/ClockListTransform.scala
@@ -13,7 +13,6 @@ import ClockListUtils._
 import Utils._
 import memlib.AnalysisUtils._
 import memlib._
-import Mappers._
 import firrtl.options.RegisteredTransform
 import scopt.OptionParser
 import firrtl.stage.RunFirrtlTransformAnnotation
diff --git a/src/main/scala/firrtl/passes/clocklist/ClockListUtils.scala b/src/main/scala/firrtl/passes/clocklist/ClockListUtils.scala
index 892f1642..2cc3dd5c 100644
--- a/src/main/scala/firrtl/passes/clocklist/ClockListUtils.scala
+++ b/src/main/scala/firrtl/passes/clocklist/ClockListUtils.scala
@@ -13,7 +13,6 @@ import ClockListUtils._
 import Utils._
 import memlib.AnalysisUtils._
 import memlib._
-import Mappers._
 
 object ClockListUtils {
   /** Returns a list of clock outputs from instances of external modules
diff --git a/src/main/scala/firrtl/passes/memlib/VerilogMemDelays.scala b/src/main/scala/firrtl/passes/memlib/VerilogMemDelays.scala
index 5bdb880d..f06ca61a 100644
--- a/src/main/scala/firrtl/passes/memlib/VerilogMemDelays.scala
+++ b/src/main/scala/firrtl/passes/memlib/VerilogMemDelays.scala
@@ -7,6 +7,7 @@ import firrtl._
 import firrtl.ir._
 import firrtl.Utils._
 import firrtl.Mappers._
+import firrtl.traversals.Foreachers._
 import firrtl.PrimOps._
 import MemPortUtils._
 
@@ -20,15 +21,10 @@ object VerilogMemDelays extends Pass {
   private def NOT(e: Expression) = DoPrim(Not, Seq(e), Nil, BoolType)
   private def AND(e1: Expression, e2: Expression) = DoPrim(And, Seq(e1, e2), Nil, BoolType)
 
-  def buildNetlist(netlist: Netlist)(s: Statement): Statement = {
-    s match {
-      case Connect(_, loc, expr) => kind(loc) match {
-        case MemKind => netlist(loc) = expr
-        case _ =>
-      }
-      case _ =>
-    }
-    s map buildNetlist(netlist)
+  def buildNetlist(netlist: Netlist)(s: Statement): Unit = s match {
+    case Connect(_, loc, expr) if (kind(loc) == MemKind) => netlist(loc) = expr
+    case _ =>
+    s.foreach(buildNetlist(netlist))
   }
 
   def memDelayStmt(
@@ -154,8 +150,8 @@ object VerilogMemDelays extends Pass {
     val namespace = Namespace(m)
     val repl = new Netlist
     val extraStmts = mutable.ArrayBuffer.empty[Statement]
-    m.map(buildNetlist(netlist))
-     .map(memDelayStmt(netlist, namespace, repl, extraStmts))
+    m.foreach(buildNetlist(netlist))
+    m.map(memDelayStmt(netlist, namespace, repl, extraStmts))
      .map(replaceStmt(repl))
      .map(appendStmts(extraStmts))
   }
diff --git a/src/main/scala/firrtl/passes/wiring/WiringUtils.scala b/src/main/scala/firrtl/passes/wiring/WiringUtils.scala
index c5a7f21b..aa698c02 100644
--- a/src/main/scala/firrtl/passes/wiring/WiringUtils.scala
+++ b/src/main/scala/firrtl/passes/wiring/WiringUtils.scala
@@ -7,6 +7,7 @@ import firrtl._
 import firrtl.ir._
 import firrtl.Utils._
 import firrtl.Mappers._
+import firrtl.traversals.Foreachers._
 import scala.collection.mutable
 import firrtl.annotations._
 import firrtl.annotations.AnnotationUtils._
@@ -84,18 +85,16 @@ object WiringUtils {
   @deprecated("Use DiGraph/InstanceGraph", "1.1.1")
   def getChildrenMap(c: Circuit): ChildrenMap = {
     val childrenMap = new ChildrenMap()
-    def getChildren(mname: String)(s: Statement): Statement = s match {
+    def getChildren(mname: String)(s: Statement): Unit = s match {
       case s: WDefInstance =>
         childrenMap(mname) = childrenMap(mname) :+ (s.name, s.module)
-        s
       case s: DefInstance =>
         childrenMap(mname) = childrenMap(mname) :+ (s.name, s.module)
-        s
-      case s => s map getChildren(mname)
+      case s => s.foreach(getChildren(mname))
     }
     c.modules.foreach{ m =>
       childrenMap(m.name) = Nil
-      m map getChildren(m.name)
+      m.foreach(getChildren(m.name))
     }
     childrenMap
   }
diff --git a/src/main/scala/firrtl/transforms/CheckCombLoops.scala b/src/main/scala/firrtl/transforms/CheckCombLoops.scala
index 1a5861c5..7afce210 100644
--- a/src/main/scala/firrtl/transforms/CheckCombLoops.scala
+++ b/src/main/scala/firrtl/transforms/CheckCombLoops.scala
@@ -10,7 +10,7 @@ import annotation.tailrec
 import firrtl._
 import firrtl.ir._
 import firrtl.passes.{Errors, PassException}
-import firrtl.Mappers._
+import firrtl.traversals.Foreachers._
 import firrtl.annotations._
 import firrtl.Utils.throwInternalError
 import firrtl.graph.{MutableDiGraph,DiGraph}
@@ -86,21 +86,15 @@ class CheckCombLoops extends Transform with RegisteredTransform {
   }
 
 
-  private def getExprDeps(deps: MutableDiGraph[LogicNode], v: LogicNode)(e: Expression): Expression = e match {
-    case r: WRef =>
-      deps.addEdgeIfValid(v, toLogicNode(r))
-      r
-    case s: WSubField =>
-      deps.addEdgeIfValid(v, toLogicNode(s))
-      s
-    case _ =>
-      e map getExprDeps(deps, v)
+  private def getExprDeps(deps: MutableDiGraph[LogicNode], v: LogicNode)(e: Expression): Unit = e match {
+    case r: WRef => deps.addEdgeIfValid(v, toLogicNode(r))
+    case s: WSubField => deps.addEdgeIfValid(v, toLogicNode(s))
+    case _ => e.foreach(getExprDeps(deps, v))
   }
 
   private def getStmtDeps(
     simplifiedModules: mutable.Map[String,DiGraph[LogicNode]],
-    deps: MutableDiGraph[LogicNode])(s: Statement): Statement = {
-    s match {
+    deps: MutableDiGraph[LogicNode])(s: Statement): Unit = s match {
       case Connect(_,loc,expr) =>
         val lhs = toLogicNode(loc)
         if (deps.contains(lhs)) {
@@ -123,9 +117,7 @@ class CheckCombLoops extends Transform with RegisteredTransform {
         iGraph.getVertices.foreach(deps.addVertex(_))
         iGraph.getVertices.foreach({ v => iGraph.getEdges(v).foreach { deps.addEdge(v,_) } })
       case _ =>
-        s map getStmtDeps(simplifiedModules,deps)
-    }
-    s
+        s.foreach(getStmtDeps(simplifiedModules,deps))
   }
 
   /*
@@ -211,7 +203,7 @@ class CheckCombLoops extends Transform with RegisteredTransform {
     for (m <- topoSortedModules) {
       val internalDeps = new MutableDiGraph[LogicNode]
       m.ports.foreach({ p => internalDeps.addVertex(LogicNode(p.name)) })
-      m map getStmtDeps(simplifiedModuleGraphs, internalDeps)
+      m.foreach(getStmtDeps(simplifiedModuleGraphs, internalDeps))
       val moduleGraph = DiGraph(internalDeps)
       moduleGraphs(m.name) = moduleGraph
       simplifiedModuleGraphs(m.name) = moduleGraphs(m.name).simplify((m.ports map { p => LogicNode(p.name) }).toSet)
diff --git a/src/test/scala/firrtlTests/CInferMDirSpec.scala b/src/test/scala/firrtlTests/CInferMDirSpec.scala
index a0f55794..db8739fd 100644
--- a/src/test/scala/firrtlTests/CInferMDirSpec.scala
+++ b/src/test/scala/firrtlTests/CInferMDirSpec.scala
@@ -6,7 +6,6 @@ import firrtl._
 import firrtl.ir._
 import firrtl.passes._
 import firrtl.transforms._
-import firrtl.Mappers._
 import annotations._
 
 class CInferMDir extends LowTransformSpec {
diff --git a/src/test/scala/firrtlTests/CheckCombLoopsSpec.scala b/src/test/scala/firrtlTests/CheckCombLoopsSpec.scala
index ed498180..8fc7dda9 100644
--- a/src/test/scala/firrtlTests/CheckCombLoopsSpec.scala
+++ b/src/test/scala/firrtlTests/CheckCombLoopsSpec.scala
@@ -6,7 +6,6 @@ import firrtl._
 import firrtl.ir._
 import firrtl.passes._
 import firrtl.transforms._
-import firrtl.Mappers._
 import annotations._
 import java.io.File
 import java.nio.file.Paths
diff --git a/src/test/scala/firrtlTests/ProtoBufSpec.scala b/src/test/scala/firrtlTests/ProtoBufSpec.scala
index 2a60eab5..ff266f1f 100644
--- a/src/test/scala/firrtlTests/ProtoBufSpec.scala
+++ b/src/test/scala/firrtlTests/ProtoBufSpec.scala
@@ -7,7 +7,6 @@ import java.io.{ByteArrayInputStream, ByteArrayOutputStream}
 import firrtl.FirrtlProtos.Firrtl
 import firrtl._
 import firrtl.ir._
-import firrtl.Mappers._
 
 class ProtoBufSpec extends FirrtlFlatSpec {