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authorAlbert Magyar2018-11-26 16:19:44 -0800
committerGitHub2018-11-26 16:19:44 -0800
commitbeba4398edeb67624ad010b7ee13f8b863f8478f (patch)
treea5b7a875a48b6c0426502aa14a0c664c375f8978 /src
parent27afc3d8defd9e2a85d5e3d2f9d2b35310b9b775 (diff)
Make return types of util functions more specific (#949)
Diffstat (limited to 'src')
-rw-r--r--src/main/scala/firrtl/Utils.scala2
-rw-r--r--src/main/scala/firrtl/passes/memlib/MemUtils.scala2
2 files changed, 2 insertions, 2 deletions
diff --git a/src/main/scala/firrtl/Utils.scala b/src/main/scala/firrtl/Utils.scala
index 44b16bf8..f60d68b1 100644
--- a/src/main/scala/firrtl/Utils.scala
+++ b/src/main/scala/firrtl/Utils.scala
@@ -419,7 +419,7 @@ object Utils extends LazyLogging {
}
}
- def module_type(m: DefModule): Type = BundleType(m.ports map {
+ def module_type(m: DefModule): BundleType = BundleType(m.ports map {
case Port(_, name, dir, tpe) => Field(name, to_flip(dir), tpe)
})
def sub_type(v: Type): Type = v match {
diff --git a/src/main/scala/firrtl/passes/memlib/MemUtils.scala b/src/main/scala/firrtl/passes/memlib/MemUtils.scala
index 709e57af..9328dfe4 100644
--- a/src/main/scala/firrtl/passes/memlib/MemUtils.scala
+++ b/src/main/scala/firrtl/passes/memlib/MemUtils.scala
@@ -63,7 +63,7 @@ object MemPortUtils {
)
// Todo: merge it with memToBundle
- def memType(mem: DefMemory): Type = {
+ def memType(mem: DefMemory): BundleType = {
val rType = BundleType(defaultPortSeq(mem) :+
Field("data", Flip, mem.dataType))
val wType = BundleType(defaultPortSeq(mem) ++ Seq(