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2020-03-12Add out-of-bounds literal access test for ReplaceAccessesAlbert Magyar
2020-03-12Avoid generating out-of-bounds indices in ReplaceAccessesAlbert Magyar
2020-03-11Don't const-prop a register's self-init (#1441)Albert Magyar
* Fixes #1214 Co-authored-by: Jack Koenig <koenig@sifive.com>
2020-03-11Migrate to DependencyAPISchuyler Eldridge
Co-authored-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> Co-authored-by: Albert Magyar <albert.magyar@gmail.com> Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-03-11Remove dead passes.DeadCodeElimination code (#1440)Albert Magyar
2020-03-10Fix copy-paste error in DiGraph.linearize documentation (#1324)Sahand Kashani-Akhavan
Co-authored-by: Albert Magyar <albert.magyar@gmail.com>
2020-03-09Provide an annotation mix-in that marks RTs as dontTouch (#1433)David Biancolin
* Provide an annotation mix-in that marks RTs as dontTouch * Update src/main/scala/firrtl/transforms/OptimizationAnnotations.scala Co-Authored-By: Albert Magyar <albert.magyar@gmail.com> * Update src/test/scala/firrtlTests/DCETests.scala Co-Authored-By: Albert Magyar <albert.magyar@gmail.com> * Update src/main/scala/firrtl/transforms/OptimizationAnnotations.scala * Update OptimizationAnnotations.scala Co-authored-by: Albert Magyar <albert.magyar@gmail.com>
2020-03-07Add firrtl-json serializers (#1430)Adam Izraelevitz
* Add firrtl-json serializers * Added support for ports, info. Added docs and tests
2020-03-06Check sign of primop constants where appropriate (#1421)Albert Magyar
* Avoid IndexOutOfBoundsException when Bits has too few consts * Check for negative consts in all relevant primops * Use BigInt for all checks on primop constants
2020-03-04Incorporate new AddNot formal regression testAlbert Magyar
* Feedback from @jackkoening * Merge into same stage as Ops to avoid Travis delays
2020-03-04Revert "Verilog emitter transform InlineNots (#1270)"Albert Magyar
This reverts commit f77487d37bd7c61be231a8000a3197d37cf55499.
2020-03-04Remove RenameMap logging from EliminateTargetPaths (#1416)Jack Koenig
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-03-03Fix error message for NegWidthException (#1418)Albert Magyar
2020-03-02Remove DiGraph.seededLinearize (#1413)Schuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-03-02Remove new unreachables in EliminateTargetPathsSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-02-20Don't add ResolvePaths annotations if no targets (#1392)Schuyler Eldridge
Adds a case to CircuitState.resolvePaths such that if no targets are requested, then no ResolvePaths annotations are added. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-02-19Add optionalPrerequisites to Dependency APISchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-02-19Add dependency prettyPrint, visualization updatesSchuyler Eldridge
This adds a prettyPrint method to the DependencyManager to enable textual visualization of the TransformLikes that a DependencyManager determines need to be run. This also cleans up the GraphViz visualization with better edge coloring and now uses the `name` method when labeling graphviz nodes. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-02-19Make PreservesAll invalidates finalSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-02-19Add additional PhaseManager testsSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-02-19Support Singleton Dependencies (#1275)Albert Magyar
This makes a change to the Dependency API that breaks chisel3. This needs to [skip chisel tests], but is fixed with https://github.com/freechipsproject/chisel3/pull/1270. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-02-18Add test case for reachableFrom behavior w.r.t. including rootAlbert Magyar
2020-02-18Update reachableFrom ScalaDocAlbert Magyar
2020-02-18Revert "Repl seq mem renaming (#1286)" (#1399)Jack Koenig
This reverts commit eabc38559b7634ff7147aa0ab3d71e78558d5162.
2020-02-18Remove last connect semantics from reset inference (#1396)Jack Koenig
* Revert "Infer resets last connect semantics (#1291)" * Fix handling of invalidated and undriven components of type Reset * Run CheckTypes after InferResets * Make reset inference bidirectional on connect * Support AsyncResetType in RemoveValidIf * Fix InferResets for parent constraints on child ports * Apply suggestions from code review * Add ScalaDoc to InferResets Co-authored-by: Albert Magyar <albert.magyar@gmail.com> Co-authored-by: Schuyler Eldridge <schuyler.eldridge@gmail.com>
2020-02-13Update ScalaTest deprecations. (#1382)Jim Lawson
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-02-13Constant prop binary PrimOps with matching argumentsAlbert Magyar
* Add SimplifyBinaryOp trait * Add extra functionality to comparison folding * Add tests * Fix comments from review
2020-02-13Add tests for (Un)?reachable InstanceGraph MethodsSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-02-13Add InstanceGraph helpers: reachable/unreachableSchuyler Eldridge
Adds new APIs for querying sets of modules in an InstanceGraph: - modules: the set of all modules - reachableModules: set of modules reachable from the main/top - unreachableModules: set of modules not reachable from the main/top Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-02-12Add test of RenameMap not recording same renameSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-02-12Add test of RenameMap self-renamingSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-02-12Update RenameMap Scaladoc for self-rename, distincSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-02-12Record self-renames in RenameMap, distinct renamesSchuyler Eldridge
Change the behavior of RenameMap.completeTarget so that self-renames do not silently *not* happen. Previously, requests to self-rename would be ignored unless they were packaged in a sequences of renames that included a self-rename. Change renames to be recorded distinctly so that multiple requests to rename to the same thing will now deduplicate. Previously, these renames would be recorded multiple times. This change was required because allowing self-renames exposed a bug in InferWidthsAnnosSpec due to multiple renames. These changes benefit the situation where you rightly want to do a self-rename. Namely, when doing module duplication (with the EliminateTargetPaths transform). Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> Do not record the same rename multiple times Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-02-12Repl seq mem renaming (#1286)Jack Koenig
* Consume NoDedupMemAnnotations in ResolveMemoryReference The ComponentName being pointed to by the annotation no longer exists after ReplaceSeqMems so we should consume the annotations * Support renaming in ReplaceMemMacros Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-02-11Add InstanceGraph.staticInstanceCount testsSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-02-11Report dead modules in staticInstanceCountSchuyler Eldridge
Change InstanceGraph.staticInstanceCount to include modules with no instances. Previously, these modules would just not be included. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-02-12Removed unused imports in src/test/ (#1381)Jim Lawson
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-02-12Fixing lint error: x + -1 (#1374)Adam Izraelevitz
* Generates lint-clean Verilog for the case: x + -1 ...where x is anything and 1 is any literal. Master behavior: input x : SInt<8> output z : SInt<9> z <= add(x, SInt(-2)) generates assign z = $signed(x) + -8'sh2; After this PR: assign z = $signed(x) - 8'sh2; If the literal is the maximum possible literal, a special case is triggered to properly trim the resulting subtraction. Input: input x : SInt<2> output z : SInt<3> z <= add(x, SInt(-2)) now generates (after this PR) assign z = $signed(x) - 3'sh2; * Updated documentation * Change ArrayBuffer to ListBuffer * Change name to minNegValue * Remove mutable public interfaces Co-authored-by: Albert Magyar <albert.magyar@gmail.com> Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-02-12Support MemConfs with very deep memories (#1367)Jerry Zhao
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-02-10Test EliminateTargetPaths ModuleTarget anno dupingSchuyler Eldridge
Add a test that EliminateTargetPaths properly duplicates an annotation pointing at a ModuleTarget. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-02-10Rename modules when duplicating instancesSchuyler Eldridge
Change the behavior of EliminateTargetPaths to generate ModuleTarget renames when instances are duplicated. Previously, only InstanceTarget renames would be generated. In effect, annotations targeting a duplicated module when be duplicated to point at the original and duplicated module. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-02-10Add Target utility referringModuleSchuyler Eldridge
This adds a utility method, referringModule, to the Target object that behaves like IsMember.pathlessTarget except that it returns the module of an InstanceTarget. This is useful for situations where you want to get at "the module" a target is pointing at, but you want behavior to get an actual module from an instance. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-02-07Add extra 'de-optimization' opportunity for register const prop testAlbert Magyar
2020-02-07Refactor handling of reg const prop entries to cover more casesAlbert Magyar
2020-02-06Better register const prop through speculative de-optimizationAlbert Magyar
* Fixes #1240 * Add failing reg const prop test case from #1240
2020-02-06Add constant prop to async regs (#1355)Adam Izraelevitz
* Add constant prop to async regs * Added another test of no reset value but constant assignment * Clarify name of updateNodeMap * Update constant assignment of async reset to not be inferred as a latch, works with donttouch * Revert "Update constant assignment of async reset to not be inferred as a latch, works with donttouch" This reverts commit 952bf38127cb32f814496a2b4b3bfb173d532728.
2020-02-06[Behavior change] Andr of zero-width wire now returns UIntLiteral(1)Albert Magyar
* Fixes #1344
2020-02-06Emit 'else' case for trivial-valued async reset regs to avoid latches (#1359)Albert Magyar
2020-02-03Dedup: check if moduleOpt exists before getting (#1323)Albert Chen
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-02-03Fix conversion of Reference-containing expressions to ReferenceTargets (#1349)Albert Magyar
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