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authorSchuyler Eldridge2020-02-12 16:52:35 -0500
committerSchuyler Eldridge2020-02-12 19:54:40 -0500
commit00e736fb1dffd7fa1cd9986dbfb3dcdb4b273fbc (patch)
treecdb50ec5a91c42d6f7081bbcfb21cddb6dffd2f1 /src
parent94c84eb1708233454cde7a752483fa1f87513ccc (diff)
Add test of RenameMap self-renaming
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
Diffstat (limited to 'src')
-rw-r--r--src/test/scala/firrtlTests/RenameMapSpec.scala14
1 files changed, 14 insertions, 0 deletions
diff --git a/src/test/scala/firrtlTests/RenameMapSpec.scala b/src/test/scala/firrtlTests/RenameMapSpec.scala
index 2da10b7f..bbe0255f 100644
--- a/src/test/scala/firrtlTests/RenameMapSpec.scala
+++ b/src/test/scala/firrtlTests/RenameMapSpec.scala
@@ -752,4 +752,18 @@ class RenameMapSpec extends FirrtlFlatSpec {
Some(Seq(bar2))
}
}
+
+ it should "record a self-rename" in {
+ val top = CircuitTarget("Top").module("Top")
+ val foo = top.instOf("foo", "Mod")
+ val bar = top.instOf("bar", "Mod")
+
+ val r = RenameMap()
+
+ r.record(foo, bar)
+ r.record(foo, foo)
+
+ r.get(foo) should not be (empty)
+ r.get(foo).get should contain allOf (foo, bar)
+ }
}