diff options
| author | Schuyler Eldridge | 2020-02-12 16:52:53 -0500 |
|---|---|---|
| committer | Schuyler Eldridge | 2020-02-12 19:54:40 -0500 |
| commit | 1909e216b8e7748d97ac34d91b18ec0f54fde46a (patch) | |
| tree | 917554e156a798242cd635ea5b6e5b978b10f019 /src | |
| parent | 00e736fb1dffd7fa1cd9986dbfb3dcdb4b273fbc (diff) | |
Add test of RenameMap not recording same rename
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/test/scala/firrtlTests/RenameMapSpec.scala | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/src/test/scala/firrtlTests/RenameMapSpec.scala b/src/test/scala/firrtlTests/RenameMapSpec.scala index bbe0255f..dc091b0a 100644 --- a/src/test/scala/firrtlTests/RenameMapSpec.scala +++ b/src/test/scala/firrtlTests/RenameMapSpec.scala @@ -766,4 +766,18 @@ class RenameMapSpec extends FirrtlFlatSpec { r.get(foo) should not be (empty) r.get(foo).get should contain allOf (foo, bar) } + + it should "not record the same rename multiple times" in { + val top = CircuitTarget("Top").module("Top") + val foo = top.instOf("foo", "Mod") + val bar = top.instOf("bar", "Mod") + + val r = RenameMap() + + r.record(foo, bar) + r.record(foo, bar) + + r.get(foo) should not be (empty) + r.get(foo).get should contain theSameElementsAs Seq(bar) + } } |
