From 1909e216b8e7748d97ac34d91b18ec0f54fde46a Mon Sep 17 00:00:00 2001 From: Schuyler Eldridge Date: Wed, 12 Feb 2020 16:52:53 -0500 Subject: Add test of RenameMap not recording same rename Signed-off-by: Schuyler Eldridge --- src/test/scala/firrtlTests/RenameMapSpec.scala | 14 ++++++++++++++ 1 file changed, 14 insertions(+) (limited to 'src') diff --git a/src/test/scala/firrtlTests/RenameMapSpec.scala b/src/test/scala/firrtlTests/RenameMapSpec.scala index bbe0255f..dc091b0a 100644 --- a/src/test/scala/firrtlTests/RenameMapSpec.scala +++ b/src/test/scala/firrtlTests/RenameMapSpec.scala @@ -766,4 +766,18 @@ class RenameMapSpec extends FirrtlFlatSpec { r.get(foo) should not be (empty) r.get(foo).get should contain allOf (foo, bar) } + + it should "not record the same rename multiple times" in { + val top = CircuitTarget("Top").module("Top") + val foo = top.instOf("foo", "Mod") + val bar = top.instOf("bar", "Mod") + + val r = RenameMap() + + r.record(foo, bar) + r.record(foo, bar) + + r.get(foo) should not be (empty) + r.get(foo).get should contain theSameElementsAs Seq(bar) + } } -- cgit v1.2.3