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authorSchuyler Eldridge2020-02-07 14:59:27 -0500
committerSchuyler Eldridge2020-02-10 12:57:50 -0500
commitbcbe60dec0c92b22f7aa98669cdec21c3111acd4 (patch)
tree78f40aed32968ec2c26f2c58bcfb7b8bd5fec7c4 /src
parent64762d2e064917233b24d193e487fc6a03f11ad2 (diff)
Test EliminateTargetPaths ModuleTarget anno duping
Add a test that EliminateTargetPaths properly duplicates an annotation pointing at a ModuleTarget. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
Diffstat (limited to 'src')
-rw-r--r--src/test/scala/firrtlTests/annotationTests/EliminateTargetPathsSpec.scala24
1 files changed, 24 insertions, 0 deletions
diff --git a/src/test/scala/firrtlTests/annotationTests/EliminateTargetPathsSpec.scala b/src/test/scala/firrtlTests/annotationTests/EliminateTargetPathsSpec.scala
index 7aac277f..9d7df718 100644
--- a/src/test/scala/firrtlTests/annotationTests/EliminateTargetPathsSpec.scala
+++ b/src/test/scala/firrtlTests/annotationTests/EliminateTargetPathsSpec.scala
@@ -372,4 +372,28 @@ class EliminateTargetPathsSpec extends FirrtlPropSpec with FirrtlMatchers {
.annotations
.collect{ case a: firrtl.annotations.transforms.ResolvePaths => a } should be (empty)
}
+
+ property("It should rename module annotations") {
+ val input =
+ """|circuit Foo:
+ | module Bar:
+ | node x = UInt<1>(0)
+ | skip
+ | module Foo:
+ | inst bar of Bar""".stripMargin
+ val Bar_x = CircuitTarget("Foo").module("Bar").ref("x")
+ val output = CircuitState(passes.ToWorkingIR.run(Parser.parse(input)), UnknownForm, Seq(DontTouchAnnotation(Bar_x)))
+ .resolvePaths(Seq(CircuitTarget("Foo").module("Foo").instOf("bar", "Bar")))
+
+ info(output.circuit.serialize)
+
+ val newBar_x = CircuitTarget("Foo").module("Bar___Foo_bar").ref("x")
+
+ output
+ .annotations
+ .filter{
+ case _: DeletedAnnotation => false
+ case _ => true
+ } should contain (DontTouchAnnotation(newBar_x))
+ }
}