Add out-of-bounds literal access test for ReplaceAccesses

1 files changed, 23 insertions, 2 deletions

diff --git a/src/test/scala/firrtlTests/ReplaceAccessesSpec.scala b/src/test/scala/firrtlTests/ReplaceAccessesSpec.scala
index ca20c90e..5b1e39dc 100644
--- a/src/test/scala/firrtlTests/ReplaceAccessesSpec.scala
+++ b/src/test/scala/firrtlTests/ReplaceAccessesSpec.scala
@@ -27,7 +27,7 @@ class ReplaceAccessesMultiDim extends ReplaceAccessesSpec {
   module Top :
     input clock : Clock
     output out : UInt<1>
-    reg r_vec : UInt<1>[4][2], clock
+    reg r_vec : UInt<1>[4][3], clock
     out <= r_vec[UInt<2>(2)][UInt<1>(1)]
 """
     val check =
@@ -35,10 +35,31 @@ class ReplaceAccessesMultiDim extends ReplaceAccessesSpec {
   module Top :
     input clock : Clock
     output out : UInt<1>
-    reg r_vec : UInt<1>[4][2], clock with :
+    reg r_vec : UInt<1>[4][3], clock with :
       reset => (UInt<1>(0), r_vec)
     out <= r_vec[2][1]
 """
     (parse(exec(input))) should be (parse(check))
   }
+
+  "ReplacesAccesses" should "NOT generate out-of-bounds indices" in {
+    val input =
+      """circuit Top :
+  module Top :
+    input clock : Clock
+    output out : UInt<1>
+    reg r_vec : UInt<1>[4][2], clock
+    out <= r_vec[UInt<3>(1)][UInt<3>(8)]
+"""
+    val check =
+      """circuit Top :
+  module Top :
+    input clock : Clock
+    output out : UInt<1>
+    reg r_vec : UInt<1>[4][2], clock with :
+      reset => (UInt<1>(0), r_vec)
+    out <= r_vec[1][UInt<3>(8)]
+"""
+    (parse(exec(input))) should be (parse(check))
+  }
 }