diff options
| author | Albert Magyar | 2020-02-07 00:27:07 -0800 |
|---|---|---|
| committer | Albert Magyar | 2020-02-07 00:27:07 -0800 |
| commit | ec365cece903de078c8c673348574a7b3b2ab7d4 (patch) | |
| tree | f2881fcfc3c0cd102c68f9f6a827ea6ae8c99cce /src | |
| parent | 71240a3c832160c66483e91c85223db5b74cea2b (diff) | |
Add extra 'de-optimization' opportunity for register const prop test
Diffstat (limited to 'src')
| -rw-r--r-- | src/test/scala/firrtlTests/ConstantPropagationTests.scala | 12 |
1 files changed, 7 insertions, 5 deletions
diff --git a/src/test/scala/firrtlTests/ConstantPropagationTests.scala b/src/test/scala/firrtlTests/ConstantPropagationTests.scala index 99b8c2f0..ef52507f 100644 --- a/src/test/scala/firrtlTests/ConstantPropagationTests.scala +++ b/src/test/scala/firrtlTests/ConstantPropagationTests.scala @@ -1153,18 +1153,20 @@ class ConstantPropagationIntegrationSpec extends LowTransformSpec { """circuit Top : | module Top : | input clock : Clock - | input reset : UInt<1> | input en : UInt<1> | output out : UInt<1> - | reg r : UInt<1>, clock + | reg r1 : UInt<1>, clock + | reg r2 : UInt<1>, clock + | when en : + | r1 <= UInt<1>(1) + | r2 <= UInt<1>(0) | when en : - | r <= UInt<1>(1) - | out <= r""".stripMargin + | r2 <= r2 + | out <= xor(r1, r2)""".stripMargin val check = """circuit Top : | module Top : | input clock : Clock - | input reset : UInt<1> | input en : UInt<1> | output out : UInt<1> | out <= UInt<1>("h1")""".stripMargin |
