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2015-10-15Added infer-types pass, seems to work. Added infer-types error checking, modi...Jack
2015-10-14Modified getType to return Type rather than Option[Type] which makes more sen...Jack
2015-10-14Moved Logger to new private object DebugUtils, changed UInt/SInt value printi...Jack
2015-10-14Don't emit SystemVerilog keywordsAndrew Waterman
2015-10-12Added initial support for debug printing for lit based testing, most types of...Jack
2015-10-12Renamed Subindex to Index and added type information to Index and DoPrimOpJack
2015-10-12Added support for no width to mean unknown, and print nothing instead of <?> ...Jack
2015-10-12Added FIRRTL comment removal to TranslatorJack
2015-10-07Added utility map functions Stmt -> Stmt, S; Exp -> Exp, S; Exp -> Exp, EJack
2015-10-07Added Printf and Stop to firrtl. #23 #24.azidar
2015-10-06Added ability to test scala FIRRTLJack
2015-10-06Merge pull request #45 from ucb-bar/change-mem-typeAdam Izraelevitz
2015-10-02Merged in Scala implementation of FIRRTL IR, parser, and serialization (ie. A...Jack
2015-10-01Merge pull request #43 from ucb-bar/new-semanticsAndrew Waterman
2015-10-01Changed DefMemory to be a non-vector type with a size member. Necessary for A...azidar
2015-10-01Change of FIRRTL semantics!azidar
2015-09-30Moved To-Real-Ir earlier, so CheckWidth could happen before PadWidthazidar
2015-09-30Fixed naming bug where __1 was matching. Caused lots o issues.azidar
2015-09-29Fixed final bug. All tests pass. Accessors are a go.azidar
2015-09-29Added DecToIndexer/DecFromIndexer. Fixed most use cases of incorrect catching...azidar
2015-08-31Sped up low form check by not checking the type of every expression, as it is...azidar
2015-08-28Moved check type and check kind after check genderazidar
2015-08-26Fixed bug where subfields weren't entirely removedazidar
2015-08-26Fixed bug where firrtl was incorrectly judging the width of a bigint. #36 #37.azidar
2015-08-25Fix Verilog backend for mixed signed-unsigned opsAndrew Waterman
2015-08-25Fixed bug in split expression that leaked connect statements out of a conditi...azidar
2015-08-25Removed IntWidth, now only use LongWidth. Now do width inference for Constant...azidar
2015-08-25Added width check pass with tests. #22.azidar
2015-08-24Temporarily deprecated the flo backend until I fix itazidar
2015-08-24Added BigInt error if passed a string without starting with a b or hazidar
2015-08-20Added tests, cleaned up repoazidar
2015-08-20Added Poison node. Includes tests. #26.azidar
2015-08-20Added rsh to BigInt library. Const Prop now works on rsh's on constants. #19.azidar
2015-08-20Fixed bigint library to correctly extract bits from UIntValue. #19.azidar
2015-08-19Added beginning of constant propagation pass, doesn't workazidar
2015-08-19Switched to new bigint libraryazidar
2015-08-19Check Neg UInt in the parserazidar
2015-08-19Fixed width inference bug where constraints were propagating backwards.azidar
2015-08-18Fixed width inference for static shift left, #18azidar
2015-08-18Fixed verilog emission from rand to randomazidar
2015-08-18Fixed bug in MinusWidth where it was adding instead of subtracting widthsazidar
2015-08-18Fixed so its length is greater than what it connects to. Changed shr to be e...azidar
2015-08-18Emit random initialization instead of zero initialization for Verilog regazidar
2015-08-17Removed leading zeros from UInt constantsazidar
2015-08-17Fixed bug where equality between expressions was incorrect, leading toazidar
2015-08-17Added tests for shl and mem. Fixed bug in verilog output of mem size.azidar
2015-08-05Added type inference before gender checkazidar
2015-08-05Fixed bug in temp elimination.azidar
2015-08-04Added check for reading from outputs with flipsazidar
2015-08-04Added () around width printersazidar
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