diff options
| author | azidar | 2015-08-17 13:35:24 -0700 |
|---|---|---|
| committer | azidar | 2015-08-17 13:35:24 -0700 |
| commit | c7e4b472787cb9702dd4fbec53eb231bdf81b4d1 (patch) | |
| tree | 9c0e400d8f35f35c21e56440d5b36db849577aea /src | |
| parent | 3cbffd9006e156ac2f7cd61702ce7f99360fcbd0 (diff) | |
Added tests for shl and mem. Fixed bug in verilog output of mem size.
Diffstat (limited to 'src')
| -rw-r--r-- | src/main/stanza/verilog.stanza | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/main/stanza/verilog.stanza b/src/main/stanza/verilog.stanza index aa755ed5..2b091e6c 100644 --- a/src/main/stanza/verilog.stanza +++ b/src/main/stanza/verilog.stanza @@ -212,7 +212,7 @@ defn emit-module (m:InModule) : add(inits,[sym " = {" width!(type(s)) "{" rand-value "}};"]) (s:DefMemory) : val vtype = type(s) as VectorType - add(regs,["reg " get-width(type(vtype)) " " sym " [0:" size(vtype) "];"]) + add(regs,["reg " get-width(type(vtype)) " " sym " [0:" size(vtype) - 1 "];"]) add(inits,["for (initvar = 0; initvar < " size(vtype) "; initvar = initvar+1)"]) add(inits,[" " sym "[initvar] = {" width!(type(vtype)) "{" rand-value "}};"]) (s:DefNode) : |