From c7e4b472787cb9702dd4fbec53eb231bdf81b4d1 Mon Sep 17 00:00:00 2001
From: azidar
Date: Mon, 17 Aug 2015 13:35:24 -0700
Subject: Added tests for shl and mem. Fixed bug in verilog output of mem size.

---
 src/main/stanza/verilog.stanza | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'src')

diff --git a/src/main/stanza/verilog.stanza b/src/main/stanza/verilog.stanza
index aa755ed5..2b091e6c 100644
--- a/src/main/stanza/verilog.stanza
+++ b/src/main/stanza/verilog.stanza
@@ -212,7 +212,7 @@ defn emit-module (m:InModule) :
             add(inits,[sym " = {" width!(type(s)) "{" rand-value "}};"])
          (s:DefMemory) :
             val vtype = type(s) as VectorType
-            add(regs,["reg  " get-width(type(vtype)) " " sym " [0:" size(vtype) "];"])
+            add(regs,["reg  " get-width(type(vtype)) " " sym " [0:" size(vtype) - 1 "];"])
             add(inits,["for (initvar = 0; initvar < " size(vtype) "; initvar = initvar+1)"])
             add(inits,["  " sym "[initvar] = {" width!(type(vtype)) "{" rand-value "}};"])
          (s:DefNode) :
-- 
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