Added BigInt error if passed a string without starting with a b or h

3 files changed, 10 insertions, 5 deletions

diff --git a/src/main/stanza/bigint2.stanza b/src/main/stanza/bigint2.stanza
index 4657878a..ebd01652 100644
--- a/src/main/stanza/bigint2.stanza
+++ b/src/main/stanza/bigint2.stanza
@@ -109,7 +109,7 @@ public defn BigIntLit (data:Int, num-bits:Int) -> BigInt :
 
 public defn BigIntLit (data:String) -> BigInt :
   val base    = data[0]
-  val shamt   = if base == 'b': 1 else if base == 'h': 4 else: 2
+  val shamt   = if base == 'b': 1 else if base == 'h': 4 else: error("Unsupported BigInt base.")
   val digits  = substring(data, 1)
   val num-bits = length(digits) * shamt
   BigIntLit(digits,shamt,num-bits)
diff --git a/src/main/stanza/custom-compiler.stanza b/src/main/stanza/custom-compiler.stanza
index 85275c94..36a6474f 100644
--- a/src/main/stanza/custom-compiler.stanza
+++ b/src/main/stanza/custom-compiler.stanza
@@ -29,13 +29,18 @@ public defmethod passes (c:InstrumentedVerilog) -> List<Pass> :
       ExpandAccessors()
       LowerToGround()
       ExpandIndexedConnects()
+      InferTypes()
+      CheckGenders()
       ExpandWhens()
       InferWidths()
+      ;Pad()
+      ConstProp()
       SplitExp()
       ToRealIR()
-      RemoveSpecialChars()
+      ;RemoveSpecialChars()
       CheckHighForm()
       CheckLowForm()
+      CheckInitialization()
       Verilog(with-output(c))
    ]
 
diff --git a/src/main/stanza/custom-passes.stanza b/src/main/stanza/custom-passes.stanza
index 30f0b6c5..44eb6b5e 100644
--- a/src/main/stanza/custom-passes.stanza
+++ b/src/main/stanza/custom-passes.stanza
@@ -47,7 +47,7 @@ defn when-coverage (port-name:Symbol, reg-name:Symbol, instrument?:HashTable<Sym
    val sym = HashTable<Symbol,Int>(symbol-hash)
    val w1 = IntWidth(1)
    val t1 = UIntType(w1)
-   val u1 = UIntValue(BigIntLit("1"),w1)
+   val u1 = UIntValue(BigIntLit("h1"),w1)
    defn when-coverage (s:Stmt) -> Stmt :
       match(s) :
          (s:Conditionally) : 
@@ -72,17 +72,17 @@ defn when-coverage (port-name:Symbol, reg-name:Symbol, instrument?:HashTable<Sym
    if length(w-ls) != 0 :
       val reg-ref = Ref(reg-name,UIntType(IntWidth(length(w-ls))))
       ;add{logic,_} $ DefRegister(FileInfo(),name(reg-ref),type(reg-ref)) TODO add clock and reset
-      add{logic,_} $ OnReset(FileInfo(),reg-ref,UIntValue(BigIntLit("0"),IntWidth(length(w-ls))))
       for (x in w-ls, i in 0 to false) do :
          add{logic,_} $ DefWire(FileInfo(),name(x),type(x))
          add{logic,_} $ Connect(FileInfo(),x,DoPrim(BIT-SELECT-OP,list(reg-ref),list(i),UIntType(w1)))
       add{logic,_} $ Connect(FileInfo(),reg-ref,concat-all(w-ls))
+      add{logic,_} $ OnReset(FileInfo(),reg-ref,UIntValue(BigIntLit("h0"),IntWidth(length(w-ls))))
 
    val i-ls = to-list $ inst-bits
    if length(i-ls) != 0 :
       for (x in i-ls, i in 0 to false) do :
          add{logic,_} $ DefWire(FileInfo(),name(x),type(x))
-         add{logic,_} $ Connect(FileInfo(),x,UIntValue(BigIntLit("0"),UnknownWidth()))
+         add{logic,_} $ Connect(FileInfo(),x,UIntValue(BigIntLit("h0"),UnknownWidth()))
 
    if instrument?[name(m)] : add{logic,_} $ Connect(FileInfo(),port-ref,concat-all(append(w-ls,i-ls)))