Emit random initialization instead of zero initialization for Verilog reg

1 files changed, 1 insertions, 1 deletions

diff --git a/src/main/stanza/verilog.stanza b/src/main/stanza/verilog.stanza
index 2b091e6c..e8c5cb45 100644
--- a/src/main/stanza/verilog.stanza
+++ b/src/main/stanza/verilog.stanza
@@ -189,7 +189,7 @@ defn emit-module (m:InModule) :
    val inst-ports = HashTable<Symbol,Vector<Streamable>>(symbol-hash)
 
    val sh = get-sym-hash(m)
-   val rand-value = "0"
+   val rand-value = "$rand" ;"0"
 
    for x in vdecs do :
       val sym = key(x)