From dc80d4f52a76aab8fcf0053b988658dd3857270c Mon Sep 17 00:00:00 2001
From: azidar
Date: Tue, 18 Aug 2015 15:10:17 -0700
Subject: Emit random initialization instead of zero initialization for Verilog
 reg

---
 src/main/stanza/verilog.stanza | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'src')

diff --git a/src/main/stanza/verilog.stanza b/src/main/stanza/verilog.stanza
index 2b091e6c..e8c5cb45 100644
--- a/src/main/stanza/verilog.stanza
+++ b/src/main/stanza/verilog.stanza
@@ -189,7 +189,7 @@ defn emit-module (m:InModule) :
    val inst-ports = HashTable<Symbol,Vector<Streamable>>(symbol-hash)
 
    val sh = get-sym-hash(m)
-   val rand-value = "0"
+   val rand-value = "$rand" ;"0"
 
    for x in vdecs do :
       val sym = key(x)
-- 
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