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authorazidar2015-08-19 11:11:51 -0700
committerazidar2015-08-19 11:12:27 -0700
commit4d4d18a6f358a7d0a227dcd999525eb57432eba0 (patch)
tree1d76e3c1540f2b984584bdf90afbbf77ec67519d /src
parent51411657aee01568519811659afd0316b6db346f (diff)
Fixed width inference bug where constraints were propagating backwards.
Updated tests to match. #29.
Diffstat (limited to 'src')
-rw-r--r--src/main/stanza/passes.stanza4
1 files changed, 1 insertions, 3 deletions
diff --git a/src/main/stanza/passes.stanza b/src/main/stanza/passes.stanza
index b8bd572a..89f77694 100644
--- a/src/main/stanza/passes.stanza
+++ b/src/main/stanza/passes.stanza
@@ -215,7 +215,7 @@ defn hasWidth (e:?) :
defn hasType (e:?) :
e typeof Ref|Subfield|Index|DoPrim|WRef|WSubfield
|WIndex|DefWire|DefRegister|DefMemory
- |VectorType|Port|Field
+ |VectorType|Port|Field|UIntValue|SIntValue
defn hasKind (e:?) :
e typeof WRef
@@ -1955,13 +1955,11 @@ defn gen-constraints (m:Module, h:HashTable<Symbol,Type>, v:Vector<WGeq>) -> Mod
val l = h[name(s)]
val r = gen-constraints(value(s))
add(v,WGeq(width!(l),width!(type(r))))
- add(v,WGeq(width!(type(r)),width!(l)))
DefNode(info(s),name(s),r)
(s:Connect) :
val l = gen-constraints(loc(s))
val e = gen-constraints(exp(s))
add(v,WGeq(width!(type(l)),width!(type(e))))
- add(v,WGeq(width!(type(e)),width!(type(l))))
Connect(info(s),l,e)
(s:Conditionally) :
val p = gen-constraints(pred(s))