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2020-02-18Update reachableFrom ScalaDocAlbert Magyar
2020-02-18Revert "Repl seq mem renaming (#1286)" (#1399)Jack Koenig
2020-02-18Remove last connect semantics from reset inference (#1396)Jack Koenig
2020-02-13Update ScalaTest deprecations. (#1382)Jim Lawson
2020-02-13Constant prop binary PrimOps with matching argumentsAlbert Magyar
2020-02-13Add tests for (Un)?reachable InstanceGraph MethodsSchuyler Eldridge
2020-02-13Add InstanceGraph helpers: reachable/unreachableSchuyler Eldridge
2020-02-12Add test of RenameMap not recording same renameSchuyler Eldridge
2020-02-12Add test of RenameMap self-renamingSchuyler Eldridge
2020-02-12Update RenameMap Scaladoc for self-rename, distincSchuyler Eldridge
2020-02-12Record self-renames in RenameMap, distinct renamesSchuyler Eldridge
2020-02-12Repl seq mem renaming (#1286)Jack Koenig
2020-02-11Add InstanceGraph.staticInstanceCount testsSchuyler Eldridge
2020-02-11Report dead modules in staticInstanceCountSchuyler Eldridge
2020-02-12Removed unused imports in src/test/ (#1381)Jim Lawson
2020-02-12Fixing lint error: x + -1 (#1374)Adam Izraelevitz
2020-02-12Support MemConfs with very deep memories (#1367)Jerry Zhao
2020-02-10Test EliminateTargetPaths ModuleTarget anno dupingSchuyler Eldridge
2020-02-10Rename modules when duplicating instancesSchuyler Eldridge
2020-02-10Add Target utility referringModuleSchuyler Eldridge
2020-02-07Add extra 'de-optimization' opportunity for register const prop testAlbert Magyar
2020-02-07Refactor handling of reg const prop entries to cover more casesAlbert Magyar
2020-02-06Better register const prop through speculative de-optimizationAlbert Magyar
2020-02-06Add constant prop to async regs (#1355)Adam Izraelevitz
2020-02-06[Behavior change] Andr of zero-width wire now returns UIntLiteral(1)Albert Magyar
2020-02-06Emit 'else' case for trivial-valued async reset regs to avoid latches (#1359)Albert Magyar
2020-02-03Dedup: check if moduleOpt exists before getting (#1323)Albert Chen
2020-02-03Fix conversion of Reference-containing expressions to ReferenceTargets (#1349)Albert Magyar
2020-01-28add IsModule, IsMember, CompleteTarget serializers (#1321)Albert Chen
2020-01-21Refactoring checkCatArgumentLegality (#1317)Derek Pappas
2020-01-20clean up warnings: trim unused imports (#1315)John Ingalls
2020-01-15Verilog emitter transform InlineBitExtractions (#1296)John Ingalls
2020-01-15improve the tail ir usability. (#1241)Sequencer
2020-01-15Filter ResolvePaths in EliminateTargetPaths (#1310)Schuyler Eldridge
2020-01-10Change LoggerState.globalLevel to Warn (#1307)Jim Lawson
2020-01-10Change default LogLevel to Warn (#1305)Schuyler Eldridge
2020-01-09Dedup PassTests, add NoCircuitDedupAnnotations (#1302)Schuyler Eldridge
2020-01-07Change printing of FIRRTL runtime from error to warnJack Koenig
2020-01-07Remove printlns from testsJack Koenig
2020-01-07Switch compileFirrtlTest from Driver to FirrtlStageJack Koenig
2020-01-07Redirect testing shell commands to loggerJack Koenig
2020-01-07Fix literals cast to Clocks in Print and StopJack Koenig
2020-01-07Remove unnecessary $signed casts for PrimOps in Verilog EmitterJack Koenig
2020-01-07Remove unnecessary casts in Constant PropagationJack Koenig
2020-01-06Verilog emitter transform InlineNots (#1270)John Ingalls
2020-01-06Remove incorrect --firrtl-source option (#1266)Schuyler Eldridge
2020-01-06Make EmittedAnnotation Unserializable (#1288)Schuyler Eldridge
2019-12-30Minor code cleansup in InferResetsJack Koenig
2019-12-30Respect last connect semantics in InferResetsJack Koenig
2019-12-18Improve Scaladoc (#1284)Schuyler Eldridge
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