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2021-03-11Fix CSESubAccesses for SubAccesses with flips (#2112)Jack Koenig
The flow of a LHS SubAccess node may still be SourceFlow if the type of the Vec element has a flip. Tweak the logic of CSESubAccesses to check every Expression flow while recursing instead of just the flow of the final SubAccess. Co-authored-by: Schuyler Eldridge <schuyler.eldridge@sifive.com> Co-authored-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
2021-03-09Create annotation to allow inline readmem in Verilog (#2107)Carlos Eduardo
This PR adds a new annotation allowing inline loading for memory files in Verilog code.
2021-03-09SMT Backend: model Invalid and Division by Zero with DefRandom nodes (#2104)Kevin Laeufer
This finally removes all randomization code from the transition system conversion and into a separate pass using DefRandom nodes.
2021-03-08SMT: memory port inout fields cannot be used as RHS expressions (#2105)Kevin Laeufer
* SMT: memory port inout fields cannot be used as RHS expressions * smt: add end2end check for read enable modelling
2021-03-04SMT Backend: move undefined memory behavior modelling to firrtl IR level (#2095)Kevin Laeufer
With this PR the smt backend now supports memories with more than two write ports and the conservative memory modelling can be selectively turned off with a new annotation.
2021-03-04CSE SubAccesses (#2099)Jack Koenig
Fixes n^2 performance problem when dynamically indexing Vecs of aggregate types. Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2021-03-03Fix ProtoBuf conversions for Verification IR (#2100)Deborah Soung
2021-03-02Remove Scala 2.11 (#2062)Jack Koenig
2021-03-02Fix CI Checks (#2097)Jack Koenig
Bumping Scala minor version but not bumping CI guards on the version causes tests to no longer run. Change to using startsWith(...) so that minor version bumps won't cause issues in the future. Also run ScalaFmt
2021-02-17ExpandWhens: ensure that statement names are maintained (#2082)Kevin Laeufer
2021-02-17Allow Side Effecting Statement to have Names (#2057)Kevin Laeufer
* firrtl: add optional statement labels for stop, printf, assert, assume and cover * test: parsing of statement labels * ir: ensure that name is properly retained * SymbolTable: add support for labled statements * test: parsing statement labels * test: lower types name collisions with named statements * ignore empty names * Inline: deal with named and unnamed statements * RemoveWires: treat stop, printf and verification statements as "others" * test: fix InlineInstance tests * DeadCodeEliminations: statements are now als declarations * CheckHighForm: ensure that statement names are not used as references * CheckSpec: throw error if statement name collides * add pass to automatically add missing statement names * check: make sure that two statements cannot have the same name * stmtLabel -> stmtName * scalafmt * add statement names to spec * spec: meta data -> metadata * EnsureStatementNames: explain naming algorithm * remove returns * better namespace use * ir: add CanBeReferenced trait * ir: add newline as jack requested
2021-02-16Add MustDeduplicateTransformJack Koenig
This enables marking modules as "must deduplicate". If modules marked as such do not deduplicate, the transform will create error reports and make suggestions as to why deduplication failed.
2021-02-01Deprecate ToWorkingIR (#2028)Schuyler Eldridge
* Deprecate firrtl.passes.ToWorkingIR Deprecate ToWorkingIR as it is now an identity transform. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com> * Deprecate firrtl.stage.Forms.WorkingIR Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com> * Switch from Forms.WorkingIR to Forms.MinimalHighForm Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com> Co-authored-by: Jack Koenig <koenig@sifive.com> Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2021-01-28Stop padding multiply and divide ops (#2058)Jack Koenig
Fixes bug with mul or div followed by cat. Also fixes some Verilog lint issues.
2021-01-20Add --dont-fold option to disable folding prim ops (#2040)Schuyler Eldridge
This adds a --dont-fold options (backed by a DisableFold annotation) that lets a user specify primitive operations which should never be folded. This feature lets a user disable certain folds which may be allowable in FIRRTL (or by any sane synthesis tool), but due to inane Verilog language design causes formal equivalence tools to fail due to the fold. Add a test that a user can disable `a / a -> 1` with a DisableFold(PrimOps.Div) annotation. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
2021-01-19Restore scalafmt CI check (#2047)Jack Koenig
Fix scalafmtCheckAll failures that snuck through
2021-01-19smt: run DeadCodeElimination after PropagatePresetAnnotations (#2036)Kevin Laeufer
2020-12-15Improve performance of LowerTypes renaming (#2024)Jack Koenig
This is done by having LowerTypes uses two RenameMaps instead of one for each module. There is one for renaming instance paths, and one for renaming everything within modules. Also add some utilities: * TargetUtils for dealing with InstanceTargets * RenameMap.fromInstanceRenames
2020-12-02smt: add support for uninterpreted ext modules (#1994)Kevin Laeufer
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-12-02Fix subaccess (#1984)Jiuyang Liu
* add test for RemoveAccessesSpec. * fix nested SubAccess bug. Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-11-30Add SortModules Transform (#1905)Schuyler Eldridge
* Add SortModules to transform to def-before-use Adds a new transform, SortModules, that transforms a FIRRTL circuit to enforce an invariant of modules and external modules being defined before use. This transform is left as optional in the event that a user may wish to have a quick way of getting the circuit to respect this property as may be expected of some other tool, e.g., MLIR. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com> * Add test of SortModules transform Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com> Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-11-12Fix RemoveWires handling of invalidated non-UInt wires (#1949)Jack Koenig
It would replace them with a validif node with a UIntLiteral which can lead to type errors.
2020-11-11smt: add support for write-first memories (#1948)Kevin Laeufer
2020-11-10Fix SMT Memory Bug (#1942)Kevin Laeufer
* smt: add test for write port collision * smt: add missing call to insertDummyAssignsForMemoryOutputs * smt: fix typo in write port code Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-11-09smt: ensure that all signals have a unique name (#1943)Kevin Laeufer
* smt: add tests for assert name clashes * smt: ensure unique signal names with a namespace this fixes issues #1934
2020-10-26fix for LoweringCompilersSpec.Jiuyang liu
2020-10-26fix a test not detecting verilog name conflicts.Jiuyang liu
2020-10-01Fix "fix" for negative literals > 32 bitsJack Koenig
Overflow of 32-bit Int would cause any negative literal value equal to -(2^(width % 32 - 1)) where width >= 32 to be incorrectly inverted
2020-09-30Add test for chaining RW-port rdata as wdata of another memAlbert Magyar
* Also clean up VerilogMemDelaySpec structure
2020-09-16Change to Apache 2.0 License (#1901)Chick Markley
2020-09-15Don't use ResolvedAnnotationPaths in ConstProp nor DCE (#1896)Jack Koenig
Both use EliminateTargetPaths to duplicate modules based on annotations. Currently, EliminateTargetPaths API is a little too limited so it duplicates more than it should which effectively breaks Dedup whenever DontTouchAnnotations are present. Also, make ConstProp and DCE treat all HasDontTouches as local annotations even if they are instance annotations. This is more conservative but it is generally better to preserve deduplication than to maximally optimize every instance. Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-09-14Hit connect case in DedupModuleTests (#1716)Schuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-09-09Make StageOption Unserializable (#1891)Jack Koenig
These options are generally specific to a stage and thus should not be propagating across serialization
2020-09-09Loosen inlining restrictions (#1882)Albert Chen
* test multiinfo comparison and mux cond inlining * loosen inlining conditions * fix typo * include dshlw * fix test
2020-09-06Add --pretty:no-expr-inlining to prevent expression inlining (#1869)Jack Koenig
Also rename --Wno-scala-version-warning to --warn:no-scala-version-deprecation and adopt naming convention where resulting annotation matches the CLI option
2020-09-06Support binary files in CustomFileEmission (#1887)Jack Koenig
2020-09-05Better error messages for unserializable annotations (#1885)Jack Koenig
2020-09-04Add test for mem port clock legalizationAlbert Magyar
2020-09-01InlineBooleanExpressions: test DontTouch (#1880)Albert Chen
* InlineBooleanExpressions: test DontTouch * run scalafmt
2020-08-31Emitter: add missing parenthesize calls (#1874)Albert Chen
2020-08-28Add test for InlineBooleanExpressions add-not exampleAlbert Magyar
2020-08-28Add custom transforms 'upstream' of emitter annotation in equiv testsAlbert Magyar
2020-08-28FlattenSpec: flattening a module with no instaces should be a no-op (#1868)Kevin Laeufer
* FlattenSpec: flattening a module with no instaces should be a no-op * Fix problem when flattening/inlining a lone module Fix an edge case bug in InlineInstances where a circuit containing a lone module is flattened/inlined. This now properly special cases the situation of an empty indexMap which before had to be of length >= 1. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> * Simplify rename logic in InlineInstances Co-authored-by: Jack Koenig <koenig@sifive.com> Co-authored-by: Albert Magyar <albert.magyar@gmail.com> Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> * Mea culpa Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> Co-authored-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> Co-authored-by: Jack Koenig <koenig@sifive.com> Co-authored-by: Albert Magyar <albert.magyar@gmail.com>
2020-08-28Deprecate CompilerAnnotation (#1870)Schuyler Eldridge
* CompilerAnnotation$ emits RunFirrtlTransform Change the CompilerAnnotation object to emit RunFirrtlTransformAnnotations containing the associated emitter. This requires a fix in the Driver compatibility layer to know how to enable one-file-per module emission if either a CompilerAnnotation or a RunFirrtlTransformAnnotation(_: Emitter) is present. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> * Add ConvertCompilerAnnotation phase Add a phase, ConvertCompilerAnnotation, that converts a CompilerAnnotation to a RunFirrtlTransformAnnotation. This provides a warning to the user if this path is taken. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> * Add test of ConvertCompilerAnnotation Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> * Deprecate CompilerAnnotation$, move helper methods Deprecate the CompilerAnnotation companion object and move it's private utility inside the RunFirrtlTransformAnnotation companion object. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> * Make ConvertCompilerAnnotations private[firrtl] Make this phase private to avoid adding a deprecation warning. Also, remove an unused string value. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> * Fix incorrect string in test Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> * Add test that '-X verilog', no emitter yields file Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-08-26smt: ignore clock signals when converting to transition system (#1866)Kevin Laeufer
If there is more than one clock, this will be detected and the user will be promted to run the StutteringClock transform.
2020-08-26Scalafmt check all (#1867)Kevin Laeufer
* run scalafmtAll * ci: scalafmtCheckAll to check all code instead of just the main sources
2020-08-26Emit parentheses in Verilog for nested unary ops (#1865)Jack Koenig
2020-08-25Inline Boolean Expressions (#1817)Albert Chen
The following conditions must be satisfied to inline: 1. has type Utils.BoolType 2. is bound to a DefNode with name starting with '_' 3. is bound to a DefNode with a source locator that points at the same file and line number. If it is a MultiInfo source locator, the set of file and line number pairs must be the same. Source locators may point to different column numbers. 4. InlineBooleanExpressionsMax has not been exceeded 5. is not a Mux Also updates the Verilog emitter to break up lines greater than 120 characters
2020-08-24Make ir.Serializer support custom FirrtlNodes (#1857)Jack Koenig
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-08-22Async reset tieoff bug (#1854)David Biancolin
* Elide emission of literals for async reset in sensitivity lists * Deprecate LegalizeClocksTransform Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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