Emit parentheses in Verilog for nested unary ops (#1865)

1 files changed, 18 insertions, 0 deletions

diff --git a/src/test/scala/firrtlTests/VerilogEmitterTests.scala b/src/test/scala/firrtlTests/VerilogEmitterTests.scala
index 42f0bf85..0a5c2c29 100644
--- a/src/test/scala/firrtlTests/VerilogEmitterTests.scala
+++ b/src/test/scala/firrtlTests/VerilogEmitterTests.scala
@@ -754,6 +754,24 @@ class VerilogEmitterSpec extends FirrtlFlatSpec {
     result("test \uD83D\uDE0E") should containLine("  assign z = x; // @[test \\uD83D\\uDE0E]")
 
   }
+
+  it should "emit repeated unary operators with parentheses" in {
+    val result1 = compileBody(
+      """input x : UInt<1>
+        |output z : UInt<1>
+        |z <= not(not(x))
+        |""".stripMargin
+    )
+    result1 should containLine("assign z = ~(~x);")
+
+    val result2 = compileBody(
+      """input x : UInt<8>
+        |output z : UInt<1>
+        |z <= not(andr(x))
+        |""".stripMargin
+    )
+    result2 should containLine("assign z = ~(&x);")
+  }
 }
 
 class VerilogDescriptionEmitterSpec extends FirrtlFlatSpec {