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* Fixes #2173
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Constant propagation of the Xor op folds `xor(a, SInt(0))` to
`asUInt(a)`. For comparison, Or folds to `asUInt(pad(a, W))`. This can
be a problem in the following case:
circuit Foo :
module Foo :
input a: UInt<3>
output b: UInt<4>
b <= asUInt(xor(asSInt(a), SInt<4>(0)))
This would emit the assignment as `b = a` instead of the sign-extended
`b = {{1{a[2]}},a}`.
This requires adjusting the `pad(e, t)` function use in const prop,
which currently just inserts a `Pad` prim op with the requested output
type. However, the function advertises that it pads *to the width* of
the type `t`. Some of the folds rely on this and request the padding of
a SInt<N> to the width of a UInt<M>. But the current implementation then
then actually returns a `Pad` op with type UInt<M>, instead of the
SInt<M> that was requested.
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To maintain binary compatibility, InlineAcrossCasts is just aliases to
the now deprecated InlineCasts. We can make the binary incompatible
change of renaming the class and object for 1.5.
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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* Update test to include both 'old' and 'new' read-under-write values
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* Emit readwrite ports, if applicable
* Does not change VerilogMemDelays -> no effect on default flow
* Use more single-line declare-and-assign statements for mem wires
* Update error messages for too-complex memories in VerilogEmitter
* Run scalafmt on VerilogEmitter
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This PR adds options for memory initialization inside or outside the
`ifndef SYNTHESIS` block.
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CSESubAccesses was intended to be a simple workaround for a quadratic
performance bug in RemoveAccesses but ended up having tricky corner
cases and was hard to get right. The solution to the RemoveAccesses
bug--quadratic expansion of dynamic indexes of vecs of aggreate
type--turned out to be quite simple and makes CSESubAccesses much less
useful and not worth fixing.
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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* add --no-constant-propagation to disable constant propagation
* add test
* deprecate DisableFold.
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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* Fix bug in zero-width memory removal
Correctly remove all extraneous connections to all types of memory
ports (read, write, readwrite) for zero-width memories. Previously,
only read ports were correctly handled.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
* fixup! Fix bug in zero-width memory removal
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This fixes an error with negating a negative SInt literal and a
[debatable] lint warning in Verilator when negating any value.
This behavior matches that of Chisel (which directly emits the 0 - x
already).
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Previously, InlineCasts could inline complex (ie. non-cast) Expressions
into other complex Expressions. Now it will only inline so long as there
no more than 1 complex Expression in the current nested Expression.
Co-authored-by: Albert Magyar <albert.magyar@gmail.com>
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Due to inlining of Boolean expressions, the following circuit is handled
directly by the VerilogEmitter:
input a: UInt<4>
input b: SInt<1>
output o: UInt<5>
o <= dshl(a, asUInt(cvt(b)))
Priot to this change, this could crash due to mishandling of cvt in the
logic to inject parentheses based on Verilog precedence rules.
This is a corner case, but similar bugs would drop up if we open up the
VerilogEmitter to more expression inlining.
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Previously, concatenating two SInts where one is of zero-width would
return the non-zero-width SInt. This is incorrect because the output of
Cat should be of type UInt. Now the ZeroWidth transform will introduce a
cast when removing a Cat when the argument type is non-UInt.
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The flow of a LHS SubAccess node may still be SourceFlow if the type of
the Vec element has a flip. Tweak the logic of CSESubAccesses to check
every Expression flow while recursing instead of just the flow of the
final SubAccess.
Co-authored-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
Co-authored-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
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This PR adds a new annotation allowing inline loading for memory files
in Verilog code.
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This finally removes all randomization code from the transition
system conversion and into a separate pass using DefRandom nodes.
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* SMT: memory port inout fields cannot be used as RHS expressions
* smt: add end2end check for read enable modelling
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With this PR the smt backend now supports memories
with more than two write ports and the conservative
memory modelling can be selectively turned off with
a new annotation.
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Fixes n^2 performance problem when dynamically indexing Vecs of
aggregate types.
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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Bumping Scala minor version but not bumping CI guards on the version
causes tests to no longer run. Change to using startsWith(...) so that
minor version bumps won't cause issues in the future.
Also run ScalaFmt
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* firrtl: add optional statement labels for stop, printf, assert, assume and cover
* test: parsing of statement labels
* ir: ensure that name is properly retained
* SymbolTable: add support for labled statements
* test: parsing statement labels
* test: lower types name collisions with named statements
* ignore empty names
* Inline: deal with named and unnamed statements
* RemoveWires: treat stop, printf and verification statements as "others"
* test: fix InlineInstance tests
* DeadCodeEliminations: statements are now als declarations
* CheckHighForm: ensure that statement names are not used as references
* CheckSpec: throw error if statement name collides
* add pass to automatically add missing statement names
* check: make sure that two statements cannot have the same name
* stmtLabel -> stmtName
* scalafmt
* add statement names to spec
* spec: meta data -> metadata
* EnsureStatementNames: explain naming algorithm
* remove returns
* better namespace use
* ir: add CanBeReferenced trait
* ir: add newline as jack requested
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This enables marking modules as "must deduplicate". If modules marked as
such do not deduplicate, the transform will create error reports and
make suggestions as to why deduplication failed.
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* Deprecate firrtl.passes.ToWorkingIR
Deprecate ToWorkingIR as it is now an identity transform.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
* Deprecate firrtl.stage.Forms.WorkingIR
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
* Switch from Forms.WorkingIR to Forms.MinimalHighForm
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
Co-authored-by: Jack Koenig <koenig@sifive.com>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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Fixes bug with mul or div followed by cat.
Also fixes some Verilog lint issues.
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This adds a --dont-fold options (backed by a DisableFold annotation)
that lets a user specify primitive operations which should never be
folded. This feature lets a user disable certain folds which may be
allowable in FIRRTL (or by any sane synthesis tool), but due to inane
Verilog language design causes formal equivalence tools to fail due to
the fold.
Add a test that a user can disable `a / a -> 1` with a
DisableFold(PrimOps.Div) annotation.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
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Fix scalafmtCheckAll failures that snuck through
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This is done by having LowerTypes uses two RenameMaps instead of one for
each module. There is one for renaming instance paths, and one for
renaming everything within modules.
Also add some utilities:
* TargetUtils for dealing with InstanceTargets
* RenameMap.fromInstanceRenames
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Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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* add test for RemoveAccessesSpec.
* fix nested SubAccess bug.
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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* Add SortModules to transform to def-before-use
Adds a new transform, SortModules, that transforms a FIRRTL circuit
to enforce an invariant of modules and external modules being defined
before use. This transform is left as optional in the event that a
user may wish to have a quick way of getting the circuit to respect
this property as may be expected of some other tool, e.g., MLIR.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
* Add test of SortModules transform
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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It would replace them with a validif node with a UIntLiteral which can
lead to type errors.
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* smt: add test for write port collision
* smt: add missing call to insertDummyAssignsForMemoryOutputs
* smt: fix typo in write port code
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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* smt: add tests for assert name clashes
* smt: ensure unique signal names with a namespace
this fixes issues #1934
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Overflow of 32-bit Int would cause any negative literal value equal to
-(2^(width % 32 - 1)) where width >= 32 to be incorrectly inverted
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* Also clean up VerilogMemDelaySpec structure
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Both use EliminateTargetPaths to duplicate modules based on annotations.
Currently, EliminateTargetPaths API is a little too limited so it
duplicates more than it should which effectively breaks Dedup whenever
DontTouchAnnotations are present.
Also, make ConstProp and DCE treat all HasDontTouches as local
annotations even if they are instance annotations. This is more
conservative but it is generally better to preserve deduplication than
to maximally optimize every instance.
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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These options are generally specific to a stage and thus should not be
propagating across serialization
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* test multiinfo comparison and mux cond inlining
* loosen inlining conditions
* fix typo
* include dshlw
* fix test
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