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path: root/src/test/scala/firrtlTests/fixed
AgeCommit message (Collapse)Author
2020-09-16Change to Apache 2.0 License (#1901)Chick Markley
2020-08-14All of src/ formatted with scalafmtchick
2020-07-30ir: use Serializer.serialize where possible (#1809)Kevin Laeufer
* ir: use Serializer.serialize where possible * ir.Serializer: serialize MultiInfo correctly * ir.Serializer: empty body needs to result in a skip statement The firrtl grammar requires at least one statement. * ir.Serializer: correctly serialize fixed point types and literals * Serializer: change Seq -> Iterable in order to be Scala 2.13 compatible
2020-03-17[RFC] Factor out common test classes; package them (#1412)David Biancolin
* Pull out common test utilities into a separate package * Project a fat jar for test utilities Co-authored-by: Albert Magyar <albert.magyar@gmail.com>
2020-02-12Removed unused imports in src/test/ (#1381)Jim Lawson
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2019-10-18Upstream intervals (#870)Adam Izraelevitz
Major features: - Added Interval type, as well as PrimOps asInterval, clip, wrap, and sqz. - Changed PrimOp names: bpset -> setp, bpshl -> incp, bpshr -> decp - Refactored width/bound inferencer into a separate constraint solver - Added transforms to infer, trim, and remove interval bounds - Tests for said features Plan to be released with 1.3
2019-09-16Rename gender to flowSchuyler Eldridge
The following names are changed: - gender -> flow - Gender -> Flow - MALE -> SourceFlow - FEMALE -> SinkFlow - BIGENDER -> DuplexFlow - UNKNOWNGENDER -> UnknownFlow Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-02-22Add Width Constraints with Annotations (#956)Albert Chen
* refactor InferWidths to allow for extra contraints, add InferWidthsWithAnnos * add test cases * add ResolvedAnnotationPaths trait to InferWidthsWithAnnos * remove println * cleanup tests * remove extraneous constraints * use foreachStmt instead of mapStmt * remove support for aggregates * fold InferWidthsWithAnnos into InferWidths * throw exception if ref not found, check for annos before AST walk
2018-02-27Refactor Annotations (#721)Jack Koenig
- Old Annotation renamed to deprecated LegacyAnnotation - Annotation is now a trait that can be extended - New JsonProtocol for Annotation [de]serialization - Replace AnnotationMap with AnnotationSeq - Deprecate Transform.getMyAnnotations - Update Transforms - Turn on deprecation warnings - Remove deprecated Driver.compile - Make AnnotationTests abstract with Legacy and Json subclasses - Add functionality to convert LegacyAnnotations of built-in annos This will give a noisy warning and is more of a best effort than a robust solution. Fixes #475 Closes #609
2018-02-21Change primop arg type (#587)Adam Izraelevitz
* Changed primops to not accept mixed-type args * Changed return type of sub of two uints to uint * Added negative tests * Removed rocket.fir. Manually changed RocketCore to not mix mul arg types. Added integration tests * Clarified test description and remove println * Fixed use of throwInternalError
2017-03-23Pass now subclasses Transform (#477)Adam Izraelevitz
2017-03-06Add ability to emit 1 file per module (#443)Jack Koenig
Changes Emitters to also be Transforms and use Annotations for both telling an emitter to do emission as well as getting the emitted result. Helper functions ease the use of the new interface. Also adds a FirrtlExecutionOptions field as well as a command-line option. Use of Writers in Compilers and Emitters is now deprecated.
2017-02-14Fixes #441, ConvertFixedToSInt not recursing expsAdam Izraelevitz
2017-02-12Changed fixed-point cat semantics to return uint (#436)Adam Izraelevitz
2017-01-23Add FixedType to uniqueify match statement.Paul Rigge
Add a test for cmem and smem with fixed point numbers
2016-12-08Clk2clock - rename the implicit "clk" module input "clock" (#387)Jim Lawson
* Rename implict module "clk" input to "clock". This doesn't rename all the "self-contained" test instances. nor the memory "clk" enables, nor the implict module "clk"s in the regress .fir files. * Consistency: rename implict module "clk" input to "clock" in "self-contained" test instances. This doesn't rename the memory "clk" enables, nor the implict module "clk"s in the regress .fir files.
2016-11-23Stringified annotations (#367)Adam Izraelevitz
Restricts annotations to be string-based (and thus less typesafe) Makes annotations more easily serializable and interact with Chisel
2016-11-04Cleanup license at top of every file (#364)Jack Koenig
Replace with more sensible comment to see LICENSE rather than including the whole license in every file
2016-11-04Refactor Compilers and Transformsjackkoenig
* Transform Ids now handled by Class[_ <: Transform] instead of magic numbers * Transforms define inputForm and outputForm * Custom transforms can be inserted at runtime into compiler or the Driver * Current "built-in" custom transforms handled via above mechanism * Verilog-specific passes moved to the Verilog emitter
2016-10-30Cleanup fixed point tests (#339)Jack Koenig
Change FixedPointMathSpec tests to use FlatSpec style instead of println Remove other printlns Remove vim comments at end of files
2016-10-17Add fixed point type (#322)Adam Izraelevitz
* WIP: Adding FixedType to Firrtl proper Got simple example running through width inference Checks should be ok Need to look into FixedLiteral more * Added simple test for fixed types * Added asFixedPoint to primops * Added tail case for FixedType * Added ConvertFixedToSInt.scala Added pass to MiddleToLowerFirrtl transform * Replace AsFixedType with AsSInt in fixed removal * Bugfix: constant from asFixed not deleted * Added unit test for bulk connect * Fixed partial connect bug #241 * Fixed missing case for FixedPoint in legalizeConnect * Add FixedMathSpec that demonstrates some problems with FixedPointMath * Fixed test and ConvertToSInt to pass. Negative binary points not easily supported, needs much more time to implement. * Refactored checking neg widths Make checking for negative binary points easier * Added tests for inferring many FixedType ops shl, shr, cat, bits, head, tail, setbp, shiftbp * Handle bpshl, bpshr, bpset in ConvertFixedToSInt Changed name from shiftbp -> bpshl, bpshr Change name from setbp -> bpset Added more tests * Added set binary point test that fails * Added simple test for zero binary point * gitignore fixes for antlr intermediate dir and intellij dir * removed unused imports retool the fixed point with zero binary point test * simplified example of inability to set binary point to zero * Temporary fix for zero-width binary point This fix allows for all widths to be zero, but since this is a feature I am working on next, I'm not going to bother with a more stringent check. * change version for dsp tools * Removed extra temporary file * Fixed merge bug * Fixed another merge bug * Removed commented out/unrelated files * Removed snake case