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authorAdam Izraelevitz2018-02-21 14:30:00 -0800
committerGitHub2018-02-21 14:30:00 -0800
commit65bbf155003a86cd836f7ff4a2def6af91794780 (patch)
tree49c968e051a36c323fd0a5839ea6e1432b2f56aa /src/test/scala/firrtlTests/fixed
parentedcb81a34dbf8a04d0b011aa1ca07c6e19598f23 (diff)
Change primop arg type (#587)
* Changed primops to not accept mixed-type args * Changed return type of sub of two uints to uint * Added negative tests * Removed rocket.fir. Manually changed RocketCore to not mix mul arg types. Added integration tests * Clarified test description and remove println * Fixed use of throwInternalError
Diffstat (limited to 'src/test/scala/firrtlTests/fixed')
-rw-r--r--src/test/scala/firrtlTests/fixed/FixedTypeInferenceSpec.scala8
1 files changed, 3 insertions, 5 deletions
diff --git a/src/test/scala/firrtlTests/fixed/FixedTypeInferenceSpec.scala b/src/test/scala/firrtlTests/fixed/FixedTypeInferenceSpec.scala
index 37209786..a866836f 100644
--- a/src/test/scala/firrtlTests/fixed/FixedTypeInferenceSpec.scala
+++ b/src/test/scala/firrtlTests/fixed/FixedTypeInferenceSpec.scala
@@ -197,12 +197,11 @@ class FixedTypeInferenceSpec extends FirrtlFlatSpec {
| module Unit :
| input a : Fixed<10><<2>>
| input b : Fixed<7><<3>>
- | input c : UInt<2>
| output cat : UInt
| output head : UInt
| output tail : UInt
| output bits : UInt
- | cat <= cat(a, c)
+ | cat <= cat(a, b)
| head <= head(a, 3)
| tail <= tail(a, 3)
| bits <= bits(a, 6, 3)""".stripMargin
@@ -211,12 +210,11 @@ class FixedTypeInferenceSpec extends FirrtlFlatSpec {
| module Unit :
| input a : Fixed<10><<2>>
| input b : Fixed<7><<3>>
- | input c : UInt<2>
- | output cat : UInt<12>
+ | output cat : UInt<17>
| output head : UInt<3>
| output tail : UInt<7>
| output bits : UInt<4>
- | cat <= cat(a, c)
+ | cat <= cat(a, b)
| head <= head(a, 3)
| tail <= tail(a, 3)
| bits <= bits(a, 6, 3)""".stripMargin