Upstream intervals (#870)

Major features:

- Added Interval type, as well as PrimOps asInterval, clip, wrap, and sqz.
- Changed PrimOp names: bpset -> setp, bpshl -> incp, bpshr -> decp
- Refactored width/bound inferencer into a separate constraint solver
- Added transforms to infer, trim, and remove interval bounds
- Tests for said features

Plan to be released with 1.3

2 files changed, 43 insertions, 14 deletions

diff --git a/src/test/scala/firrtlTests/fixed/FixedTypeInferenceSpec.scala b/src/test/scala/firrtlTests/fixed/FixedTypeInferenceSpec.scala
index 6bf86479..a34145ac 100644
--- a/src/test/scala/firrtlTests/fixed/FixedTypeInferenceSpec.scala
+++ b/src/test/scala/firrtlTests/fixed/FixedTypeInferenceSpec.scala
@@ -21,6 +21,36 @@ class FixedTypeInferenceSpec extends FirrtlFlatSpec {
     }
   }
 
+  "Fixed types" should "infer add correctly if only precision unspecified" in {
+    val passes = Seq(
+      ToWorkingIR,
+      CheckHighForm,
+      ResolveKinds,
+      InferTypes,
+      CheckTypes,
+      ResolveFlows,
+      CheckFlows,
+      new InferWidths,
+      CheckWidths)
+    val input =
+      """circuit Unit :
+        |  module Unit :
+        |    input a : Fixed<10><<2>>
+        |    input b : Fixed<10><<0>>
+        |    input c : Fixed<4><<3>>
+        |    output d : Fixed<13>
+        |    d <= add(a, add(b, c))""".stripMargin
+    val check =
+      """circuit Unit :
+        |  module Unit :
+        |    input a : Fixed<10><<2>>
+        |    input b : Fixed<10><<0>>
+        |    input c : Fixed<4><<3>>
+        |    output d : Fixed<13><<3>>
+        |    d <= add(a, add(b, c))""".stripMargin
+    executeTest(input, check.split("\n") map normalized, passes)
+  }
+
   "Fixed types" should "infer add correctly" in {
     val passes = Seq(
       ToWorkingIR,
@@ -36,7 +66,7 @@ class FixedTypeInferenceSpec extends FirrtlFlatSpec {
       """circuit Unit :
         |  module Unit :
         |    input a : Fixed<10><<2>>
-        |    input b : Fixed<10>
+        |    input b : Fixed<10><<0>>
         |    input c : Fixed<4><<3>>
         |    output d : Fixed
         |    d <= add(a, add(b, c))""".stripMargin
@@ -119,13 +149,13 @@ class FixedTypeInferenceSpec extends FirrtlFlatSpec {
         |  module Unit :
         |    input a : Fixed<10><<2>>
         |    output d : Fixed
-        |    d <= bpshl(a, 2)""".stripMargin
+        |    d <= incp(a, 2)""".stripMargin
     val check =
       """circuit Unit :
         |  module Unit :
         |    input a : Fixed<10><<2>>
         |    output d : Fixed<12><<4>>
-        |    d <= bpshl(a, 2)""".stripMargin
+        |    d <= incp(a, 2)""".stripMargin
     executeTest(input, check.split("\n") map normalized, passes)
   }
 
@@ -145,13 +175,13 @@ class FixedTypeInferenceSpec extends FirrtlFlatSpec {
         |  module Unit :
         |    input a : Fixed<10><<2>>
         |    output d : Fixed
-        |    d <= bpshr(a, 2)""".stripMargin
+        |    d <= decp(a, 2)""".stripMargin
     val check =
       """circuit Unit :
         |  module Unit :
         |    input a : Fixed<10><<2>>
         |    output d : Fixed<8><<0>>
-        |    d <= bpshr(a, 2)""".stripMargin
+        |    d <= decp(a, 2)""".stripMargin
     executeTest(input, check.split("\n") map normalized, passes)
   }
 
@@ -171,13 +201,13 @@ class FixedTypeInferenceSpec extends FirrtlFlatSpec {
         |  module Unit :
         |    input a : Fixed<10><<2>>
         |    output d : Fixed
-        |    d <= bpset(a, 3)""".stripMargin
+        |    d <= setp(a, 3)""".stripMargin
     val check =
       """circuit Unit :
         |  module Unit :
         |    input a : Fixed<10><<2>>
         |    output d : Fixed<11><<3>>
-        |    d <= bpset(a, 3)""".stripMargin
+        |    d <= setp(a, 3)""".stripMargin
     executeTest(input, check.split("\n") map normalized, passes)
   }
 
diff --git a/src/test/scala/firrtlTests/fixed/RemoveFixedTypeSpec.scala b/src/test/scala/firrtlTests/fixed/RemoveFixedTypeSpec.scala
index 8686bd0f..f5b16e45 100644
--- a/src/test/scala/firrtlTests/fixed/RemoveFixedTypeSpec.scala
+++ b/src/test/scala/firrtlTests/fixed/RemoveFixedTypeSpec.scala
@@ -14,7 +14,6 @@ class RemoveFixedTypeSpec extends FirrtlFlatSpec {
       (c: CircuitState, p: Transform) => p.runTransform(c)
     }.circuit
     val lines = c.serialize.split("\n") map normalized
-    println(c.serialize)
 
     expected foreach { e =>
       lines should contain(e)
@@ -37,7 +36,7 @@ class RemoveFixedTypeSpec extends FirrtlFlatSpec {
       """circuit Unit :
         |  module Unit :
         |    input a : Fixed<10><<2>>
-        |    input b : Fixed<10>
+        |    input b : Fixed<10><<0>>
         |    input c : Fixed<4><<3>>
         |    output d : Fixed<<5>>
         |    d <= add(a, add(b, c))""".stripMargin
@@ -67,7 +66,7 @@ class RemoveFixedTypeSpec extends FirrtlFlatSpec {
       """circuit Unit :
         |  module Unit :
         |    input a : Fixed<10><<2>>
-        |    input b : Fixed<10>
+        |    input b : Fixed<10><<0>>
         |    input c : Fixed<4><<3>>
         |    output d : Fixed<<5>>
         |    d <- add(a, add(b, c))""".stripMargin
@@ -99,7 +98,7 @@ class RemoveFixedTypeSpec extends FirrtlFlatSpec {
         |  module Unit :
         |    input a : Fixed<10><<2>>
         |    output d : Fixed<12><<4>>
-        |    d <= bpshl(a, 2)""".stripMargin
+        |    d <= incp(a, 2)""".stripMargin
     val check =
       """circuit Unit :
         |  module Unit :
@@ -126,7 +125,7 @@ class RemoveFixedTypeSpec extends FirrtlFlatSpec {
         |  module Unit :
         |    input a : Fixed<10><<2>>
         |    output d : Fixed<9><<1>>
-        |    d <= bpshr(a, 1)""".stripMargin
+        |    d <= decp(a, 1)""".stripMargin
     val check =
       """circuit Unit :
         |  module Unit :
@@ -153,7 +152,7 @@ class RemoveFixedTypeSpec extends FirrtlFlatSpec {
         |  module Unit :
         |    input a : Fixed<10><<2>>
         |    output d : Fixed
-        |    d <= bpset(a, 3)""".stripMargin
+        |    d <= setp(a, 3)""".stripMargin
     val check =
       """circuit Unit :
         |  module Unit :
@@ -181,7 +180,7 @@ class RemoveFixedTypeSpec extends FirrtlFlatSpec {
     class CheckChirrtlTransform extends SeqTransform {
       def inputForm = ChirrtlForm
       def outputForm = ChirrtlForm
-      val transforms = Seq(passes.CheckChirrtl)
+      def transforms = Seq(passes.CheckChirrtl)
     }
 
     val chirrtlTransform = new CheckChirrtlTransform