All of src/ formatted with scalafmt

4 files changed, 151 insertions, 124 deletions

diff --git a/src/test/scala/firrtlTests/fixed/FixedPointMathSpec.scala b/src/test/scala/firrtlTests/fixed/FixedPointMathSpec.scala
index c4de1f46..a41ac90a 100644
--- a/src/test/scala/firrtlTests/fixed/FixedPointMathSpec.scala
+++ b/src/test/scala/firrtlTests/fixed/FixedPointMathSpec.scala
@@ -2,21 +2,21 @@
 
 package firrtlTests.fixed
 
-import firrtl.{CircuitState, ChirrtlForm, LowFirrtlCompiler}
+import firrtl.{ChirrtlForm, CircuitState, LowFirrtlCompiler}
 import firrtl.testutils.FirrtlFlatSpec
 
 class FixedPointMathSpec extends FirrtlFlatSpec {
 
-  val SumPattern        = """.*output sum.*<(\d+)>.*.*""".r
-  val ProductPattern    = """.*output product.*<(\d+)>.*""".r
+  val SumPattern = """.*output sum.*<(\d+)>.*.*""".r
+  val ProductPattern = """.*output product.*<(\d+)>.*""".r
   val DifferencePattern = """.*output difference.*<(\d+)>.*""".r
 
-  val AssignPattern     = """\s*(\w+) <= (\w+)\((.*)\)\s*""".r
+  val AssignPattern = """\s*(\w+) <= (\w+)\((.*)\)\s*""".r
 
   for {
-    bits1        <- 1 to 4
+    bits1 <- 1 to 4
     binaryPoint1 <- 1 to 4
-    bits2        <- 1 to 4
+    bits2 <- 1 to 4
     binaryPoint2 <- 1 to 4
   } {
     def config = s"($bits1,$binaryPoint1)($bits2,$binaryPoint2)"
@@ -25,26 +25,26 @@ class FixedPointMathSpec extends FirrtlFlatSpec {
 
       val input =
         s"""circuit Unit :
-        |  module Unit :
-        |    input  a : Fixed<$bits1><<$binaryPoint1>>
-        |    input  b : Fixed<$bits2><<$binaryPoint2>>
-        |    output sum        : Fixed
-        |    output product    : Fixed
-        |    output difference : Fixed
-        |    sum        <= add(a, b)
-        |    product    <= mul(a, b)
-        |    difference <= sub(a, b)
-        |    """.stripMargin
+           |  module Unit :
+           |    input  a : Fixed<$bits1><<$binaryPoint1>>
+           |    input  b : Fixed<$bits2><<$binaryPoint2>>
+           |    output sum        : Fixed
+           |    output product    : Fixed
+           |    output difference : Fixed
+           |    sum        <= add(a, b)
+           |    product    <= mul(a, b)
+           |    difference <= sub(a, b)
+           |    """.stripMargin
 
       val lowerer = new LowFirrtlCompiler
 
       val res = lowerer.compileAndEmit(CircuitState(parse(input), ChirrtlForm))
 
-      val output = res.getEmittedCircuit.value split "\n"
+      val output = res.getEmittedCircuit.value.split("\n")
 
       def inferredAddWidth: Int = {
         val binaryDifference = binaryPoint1 - binaryPoint2
-        val (newW1, newW2) = if(binaryDifference > 0) {
+        val (newW1, newW2) = if (binaryDifference > 0) {
           (bits1, bits2 + binaryDifference)
         } else {
           (bits1 + binaryDifference.abs, bits2)
@@ -54,11 +54,11 @@ class FixedPointMathSpec extends FirrtlFlatSpec {
 
       for (line <- output) {
         line match {
-          case SumPattern(varWidth)     =>
+          case SumPattern(varWidth) =>
             assert(varWidth.toInt === inferredAddWidth, s"$config sum sint bits wrong for $line")
           case ProductPattern(varWidth) =>
             assert(varWidth.toInt === bits1 + bits2, s"$config product bits wrong for $line")
-          case DifferencePattern(varWidth)     =>
+          case DifferencePattern(varWidth) =>
             assert(varWidth.toInt === inferredAddWidth, s"$config difference bits wrong for $line")
           case AssignPattern(varName, operation, args) =>
             varName match {
@@ -66,11 +66,15 @@ class FixedPointMathSpec extends FirrtlFlatSpec {
                 assert(operation === "add", s"var sum should be result of an add in $line")
                 if (binaryPoint1 > binaryPoint2) {
                   assert(!args.contains("shl(a"), s"$config first arg should be just a in $line")
-                  assert(args.contains(s"shl(b, ${binaryPoint1 - binaryPoint2})"),
-                    s"$config second arg incorrect in $line")
+                  assert(
+                    args.contains(s"shl(b, ${binaryPoint1 - binaryPoint2})"),
+                    s"$config second arg incorrect in $line"
+                  )
                 } else if (binaryPoint1 < binaryPoint2) {
-                  assert(args.contains(s"shl(a, ${(binaryPoint1 - binaryPoint2).abs})"),
-                    s"$config second arg incorrect in $line")
+                  assert(
+                    args.contains(s"shl(a, ${(binaryPoint1 - binaryPoint2).abs})"),
+                    s"$config second arg incorrect in $line"
+                  )
                   assert(!args.contains("shl(b"), s"$config second arg should be just b in $line")
                 } else {
                   assert(!args.contains("shl(a"), s"$config first arg should be just a in $line")
@@ -84,11 +88,15 @@ class FixedPointMathSpec extends FirrtlFlatSpec {
                 assert(operation === "sub", s"var difference should be result of an sub in $line")
                 if (binaryPoint1 > binaryPoint2) {
                   assert(!args.contains("shl(a"), s"$config first arg should be just a in $line")
-                  assert(args.contains(s"shl(b, ${binaryPoint1 - binaryPoint2})"),
-                    s"$config second arg incorrect in $line")
+                  assert(
+                    args.contains(s"shl(b, ${binaryPoint1 - binaryPoint2})"),
+                    s"$config second arg incorrect in $line"
+                  )
                 } else if (binaryPoint1 < binaryPoint2) {
-                  assert(args.contains(s"shl(a, ${(binaryPoint1 - binaryPoint2).abs})"),
-                    s"$config second arg incorrect in $line")
+                  assert(
+                    args.contains(s"shl(a, ${(binaryPoint1 - binaryPoint2).abs})"),
+                    s"$config second arg incorrect in $line"
+                  )
                   assert(!args.contains("shl(b"), s"$config second arg should be just b in $line")
                 } else {
                   assert(!args.contains("shl(a"), s"$config first arg should be just a in $line")
@@ -102,4 +110,3 @@ class FixedPointMathSpec extends FirrtlFlatSpec {
     }
   }
 }
-
diff --git a/src/test/scala/firrtlTests/fixed/FixedSerializationSpec.scala b/src/test/scala/firrtlTests/fixed/FixedSerializationSpec.scala
index db107cb3..68125bc0 100644
--- a/src/test/scala/firrtlTests/fixed/FixedSerializationSpec.scala
+++ b/src/test/scala/firrtlTests/fixed/FixedSerializationSpec.scala
@@ -7,7 +7,7 @@ import firrtl.ir
 import org.scalatest.flatspec.AnyFlatSpec
 
 class FixedSerializationSpec extends AnyFlatSpec {
-  behavior of "FixedType"
+  behavior.of("FixedType")
 
   it should "serialize correctly" in {
     assert(ir.FixedType(ir.IntWidth(3), ir.IntWidth(2)).serialize == "Fixed<3><<2>>")
@@ -16,7 +16,7 @@ class FixedSerializationSpec extends AnyFlatSpec {
     assert(ir.FixedType(ir.UnknownWidth, ir.UnknownWidth).serialize == "Fixed")
   }
 
-  behavior of "FixedLiteral"
+  behavior.of("FixedLiteral")
 
   it should "serialize correctly" in {
     assert(ir.FixedLiteral(1, ir.IntWidth(3), ir.IntWidth(2)).serialize == "Fixed<3><<2>>(\"h1\")")
diff --git a/src/test/scala/firrtlTests/fixed/FixedTypeInferenceSpec.scala b/src/test/scala/firrtlTests/fixed/FixedTypeInferenceSpec.scala
index 1a7092bb..4d3dbe98 100644
--- a/src/test/scala/firrtlTests/fixed/FixedTypeInferenceSpec.scala
+++ b/src/test/scala/firrtlTests/fixed/FixedTypeInferenceSpec.scala
@@ -9,12 +9,14 @@ import firrtl.testutils._
 
 class FixedTypeInferenceSpec extends FirrtlFlatSpec {
   private def executeTest(input: String, expected: Seq[String], passes: Seq[Transform]) = {
-    val c = passes.foldLeft(CircuitState(Parser.parse(input.split("\n").toIterator), UnknownForm)) {
-      (c: CircuitState, p: Transform) => p.runTransform(c)
-    }.circuit
-    val lines = c.serialize.split("\n") map normalized
+    val c = passes
+      .foldLeft(CircuitState(Parser.parse(input.split("\n").toIterator), UnknownForm)) {
+        (c: CircuitState, p: Transform) => p.runTransform(c)
+      }
+      .circuit
+    val lines = c.serialize.split("\n").map(normalized)
 
-    expected foreach { e =>
+    expected.foreach { e =>
       lines should contain(e)
     }
   }
@@ -29,7 +31,8 @@ class FixedTypeInferenceSpec extends FirrtlFlatSpec {
       ResolveFlows,
       CheckFlows,
       new InferWidths,
-      CheckWidths)
+      CheckWidths
+    )
     val input =
       """circuit Unit :
         |  module Unit :
@@ -46,7 +49,7 @@ class FixedTypeInferenceSpec extends FirrtlFlatSpec {
         |    input c : Fixed<4><<3>>
         |    output d : Fixed<13><<3>>
         |    d <= add(a, add(b, c))""".stripMargin
-    executeTest(input, check.split("\n") map normalized, passes)
+    executeTest(input, check.split("\n").map(normalized), passes)
   }
 
   "Fixed types" should "infer add correctly" in {
@@ -59,7 +62,8 @@ class FixedTypeInferenceSpec extends FirrtlFlatSpec {
       ResolveFlows,
       CheckFlows,
       new InferWidths,
-      CheckWidths)
+      CheckWidths
+    )
     val input =
       """circuit Unit :
         |  module Unit :
@@ -76,7 +80,7 @@ class FixedTypeInferenceSpec extends FirrtlFlatSpec {
         |    input c : Fixed<4><<3>>
         |    output d : Fixed<15><<3>>
         |    d <= add(a, add(b, c))""".stripMargin
-    executeTest(input, check.split("\n") map normalized, passes)
+    executeTest(input, check.split("\n").map(normalized), passes)
   }
 
   "Fixed types" should "be correctly shifted left" in {
@@ -89,7 +93,8 @@ class FixedTypeInferenceSpec extends FirrtlFlatSpec {
       ResolveFlows,
       CheckFlows,
       new InferWidths,
-      CheckWidths)
+      CheckWidths
+    )
     val input =
       """circuit Unit :
         |  module Unit :
@@ -102,7 +107,7 @@ class FixedTypeInferenceSpec extends FirrtlFlatSpec {
         |    input a : Fixed<10><<2>>
         |    output d : Fixed<12><<2>>
         |    d <= shl(a, 2)""".stripMargin
-    executeTest(input, check.split("\n") map normalized, passes)
+    executeTest(input, check.split("\n").map(normalized), passes)
   }
 
   "Fixed types" should "be correctly shifted right" in {
@@ -115,7 +120,8 @@ class FixedTypeInferenceSpec extends FirrtlFlatSpec {
       ResolveFlows,
       CheckFlows,
       new InferWidths,
-      CheckWidths)
+      CheckWidths
+    )
     val input =
       """circuit Unit :
         |  module Unit :
@@ -128,7 +134,7 @@ class FixedTypeInferenceSpec extends FirrtlFlatSpec {
         |    input a : Fixed<10><<2>>
         |    output d : Fixed<8><<2>>
         |    d <= shr(a, 2)""".stripMargin
-    executeTest(input, check.split("\n") map normalized, passes)
+    executeTest(input, check.split("\n").map(normalized), passes)
   }
 
   "Fixed types" should "relatively move binary point left" in {
@@ -141,7 +147,8 @@ class FixedTypeInferenceSpec extends FirrtlFlatSpec {
       ResolveFlows,
       CheckFlows,
       new InferWidths,
-      CheckWidths)
+      CheckWidths
+    )
     val input =
       """circuit Unit :
         |  module Unit :
@@ -154,7 +161,7 @@ class FixedTypeInferenceSpec extends FirrtlFlatSpec {
         |    input a : Fixed<10><<2>>
         |    output d : Fixed<12><<4>>
         |    d <= incp(a, 2)""".stripMargin
-    executeTest(input, check.split("\n") map normalized, passes)
+    executeTest(input, check.split("\n").map(normalized), passes)
   }
 
   "Fixed types" should "relatively move binary point right" in {
@@ -167,7 +174,8 @@ class FixedTypeInferenceSpec extends FirrtlFlatSpec {
       ResolveFlows,
       CheckFlows,
       new InferWidths,
-      CheckWidths)
+      CheckWidths
+    )
     val input =
       """circuit Unit :
         |  module Unit :
@@ -180,7 +188,7 @@ class FixedTypeInferenceSpec extends FirrtlFlatSpec {
         |    input a : Fixed<10><<2>>
         |    output d : Fixed<8><<0>>
         |    d <= decp(a, 2)""".stripMargin
-    executeTest(input, check.split("\n") map normalized, passes)
+    executeTest(input, check.split("\n").map(normalized), passes)
   }
 
   "Fixed types" should "absolutely set binary point correctly" in {
@@ -193,7 +201,8 @@ class FixedTypeInferenceSpec extends FirrtlFlatSpec {
       ResolveFlows,
       CheckFlows,
       new InferWidths,
-      CheckWidths)
+      CheckWidths
+    )
     val input =
       """circuit Unit :
         |  module Unit :
@@ -206,7 +215,7 @@ class FixedTypeInferenceSpec extends FirrtlFlatSpec {
         |    input a : Fixed<10><<2>>
         |    output d : Fixed<11><<3>>
         |    d <= setp(a, 3)""".stripMargin
-    executeTest(input, check.split("\n") map normalized, passes)
+    executeTest(input, check.split("\n").map(normalized), passes)
   }
 
   "Fixed types" should "cat, head, tail, bits" in {
@@ -219,7 +228,8 @@ class FixedTypeInferenceSpec extends FirrtlFlatSpec {
       ResolveFlows,
       CheckFlows,
       new InferWidths,
-      CheckWidths)
+      CheckWidths
+    )
     val input =
       """circuit Unit :
         |  module Unit :
@@ -246,7 +256,7 @@ class FixedTypeInferenceSpec extends FirrtlFlatSpec {
         |    head <= head(a, 3)
         |    tail <= tail(a, 3)
         |    bits <= bits(a, 6, 3)""".stripMargin
-    executeTest(input, check.split("\n") map normalized, passes)
+    executeTest(input, check.split("\n").map(normalized), passes)
   }
 
   "Fixed types" should "be cast to" in {
@@ -259,7 +269,8 @@ class FixedTypeInferenceSpec extends FirrtlFlatSpec {
       ResolveFlows,
       CheckFlows,
       new InferWidths,
-      CheckWidths)
+      CheckWidths
+    )
     val input =
       """circuit Unit :
         |  module Unit :
@@ -272,7 +283,7 @@ class FixedTypeInferenceSpec extends FirrtlFlatSpec {
         |    input a : SInt<10>
         |    output d : Fixed<10><<2>>
         |    d <= asFixedPoint(a, 2)""".stripMargin
-    executeTest(input, check.split("\n") map normalized, passes)
+    executeTest(input, check.split("\n").map(normalized), passes)
   }
 
   "Fixed types" should "support binary point of zero" in {
@@ -286,7 +297,8 @@ class FixedTypeInferenceSpec extends FirrtlFlatSpec {
       CheckFlows,
       new InferWidths,
       CheckWidths,
-      ConvertFixedToSInt)
+      ConvertFixedToSInt
+    )
     val input =
       """
         |circuit Unit :
@@ -312,53 +324,53 @@ class FixedTypeInferenceSpec extends FirrtlFlatSpec {
         |    io_out <= io_in
         |
       """.stripMargin
-    executeTest(input, check.split("\n") map normalized, passes)
+    executeTest(input, check.split("\n").map(normalized), passes)
   }
   "Fixed types" should "work with mems" in {
     def input(memType: String): String =
       s"""
-        |circuit Unit :
-        |  module Unit :
-        |    input clock : Clock
-        |    input in : Fixed<16><<8>>
-        |    input ridx : UInt<3>
-        |    output out : Fixed<16><<8>>
-        |    input widx : UInt<3>
-        |    $memType mem : Fixed<16><<8>>[8]
-        |    infer mport min = mem[ridx], clock
-        |    min <= in
-        |    infer mport mout = mem[widx], clock
-        |    out <= mout
+         |circuit Unit :
+         |  module Unit :
+         |    input clock : Clock
+         |    input in : Fixed<16><<8>>
+         |    input ridx : UInt<3>
+         |    output out : Fixed<16><<8>>
+         |    input widx : UInt<3>
+         |    $memType mem : Fixed<16><<8>>[8]
+         |    infer mport min = mem[ridx], clock
+         |    min <= in
+         |    infer mport mout = mem[widx], clock
+         |    out <= mout
       """.stripMargin
     def check(readLatency: Int, moutEn: Int, minEn: Int): String =
       s"""
-        |circuit Unit :
-        |  module Unit :
-        |    input clock : Clock
-        |    input in : SInt<16>
-        |    input ridx : UInt<3>
-        |    output out : SInt<16>
-        |    input widx : UInt<3>
-        |
-        |    mem mem :
-        |      data-type => SInt<16>
-        |      depth => 8
-        |      read-latency => $readLatency
-        |      write-latency => 1
-        |      reader => mout
-        |      writer => min
-        |      read-under-write => undefined
-        |    out <= mem.mout.data
-        |    mem.mout.addr <= widx
-        |    mem.mout.en <= UInt<1>("h$moutEn")
-        |    mem.mout.clk <= clock
-        |    mem.min.addr <= ridx
-        |    mem.min.en <= UInt<1>("h$minEn")
-        |    mem.min.clk <= clock
-        |    mem.min.data <= in
-        |    mem.min.mask <= UInt<1>("h1")
+         |circuit Unit :
+         |  module Unit :
+         |    input clock : Clock
+         |    input in : SInt<16>
+         |    input ridx : UInt<3>
+         |    output out : SInt<16>
+         |    input widx : UInt<3>
+         |
+         |    mem mem :
+         |      data-type => SInt<16>
+         |      depth => 8
+         |      read-latency => $readLatency
+         |      write-latency => 1
+         |      reader => mout
+         |      writer => min
+         |      read-under-write => undefined
+         |    out <= mem.mout.data
+         |    mem.mout.addr <= widx
+         |    mem.mout.en <= UInt<1>("h$moutEn")
+         |    mem.mout.clk <= clock
+         |    mem.min.addr <= ridx
+         |    mem.min.en <= UInt<1>("h$minEn")
+         |    mem.min.clk <= clock
+         |    mem.min.data <= in
+         |    mem.min.mask <= UInt<1>("h1")
       """.stripMargin
-    executeTest(input("smem"), check(1, 0, 1).split("\n") map normalized, new LowFirrtlCompiler)
-    executeTest(input("cmem"), check(0, 1, 1).split("\n") map normalized, new LowFirrtlCompiler)
+    executeTest(input("smem"), check(1, 0, 1).split("\n").map(normalized), new LowFirrtlCompiler)
+    executeTest(input("cmem"), check(0, 1, 1).split("\n").map(normalized), new LowFirrtlCompiler)
   }
 }
diff --git a/src/test/scala/firrtlTests/fixed/RemoveFixedTypeSpec.scala b/src/test/scala/firrtlTests/fixed/RemoveFixedTypeSpec.scala
index 9dc61927..d0218b11 100644
--- a/src/test/scala/firrtlTests/fixed/RemoveFixedTypeSpec.scala
+++ b/src/test/scala/firrtlTests/fixed/RemoveFixedTypeSpec.scala
@@ -9,12 +9,14 @@ import firrtl.testutils._
 
 class RemoveFixedTypeSpec extends FirrtlFlatSpec {
   private def executeTest(input: String, expected: Seq[String], passes: Seq[Transform]) = {
-    val c = passes.foldLeft(CircuitState(Parser.parse(input.split("\n").toIterator), UnknownForm)) {
-      (c: CircuitState, p: Transform) => p.runTransform(c)
-    }.circuit
-    val lines = c.serialize.split("\n") map normalized
+    val c = passes
+      .foldLeft(CircuitState(Parser.parse(input.split("\n").toIterator), UnknownForm)) {
+        (c: CircuitState, p: Transform) => p.runTransform(c)
+      }
+      .circuit
+    val lines = c.serialize.split("\n").map(normalized)
 
-    expected foreach { e =>
+    expected.foreach { e =>
       lines should contain(e)
     }
   }
@@ -30,7 +32,8 @@ class RemoveFixedTypeSpec extends FirrtlFlatSpec {
       CheckFlows,
       new InferWidths,
       CheckWidths,
-      ConvertFixedToSInt)
+      ConvertFixedToSInt
+    )
     val input =
       """circuit Unit :
         |  module Unit :
@@ -41,13 +44,13 @@ class RemoveFixedTypeSpec extends FirrtlFlatSpec {
         |    d <= add(a, add(b, c))""".stripMargin
     val check =
       """circuit Unit :
-         |  module Unit :
-         |    input a : SInt<10>
-         |    input b : SInt<10>
-         |    input c : SInt<4>
-         |    output d : SInt<15>
-         |    d <= shl(add(shl(a, 1), add(shl(b, 3), c)), 2)""".stripMargin
-    executeTest(input, check.split("\n") map normalized, passes)
+        |  module Unit :
+        |    input a : SInt<10>
+        |    input b : SInt<10>
+        |    input c : SInt<4>
+        |    output d : SInt<15>
+        |    d <= shl(add(shl(a, 1), add(shl(b, 3), c)), 2)""".stripMargin
+    executeTest(input, check.split("\n").map(normalized), passes)
   }
   "Fixed types" should "be removed, even with a bulk connect" in {
     val passes = Seq(
@@ -60,7 +63,8 @@ class RemoveFixedTypeSpec extends FirrtlFlatSpec {
       CheckFlows,
       new InferWidths,
       CheckWidths,
-      ConvertFixedToSInt)
+      ConvertFixedToSInt
+    )
     val input =
       """circuit Unit :
         |  module Unit :
@@ -71,13 +75,13 @@ class RemoveFixedTypeSpec extends FirrtlFlatSpec {
         |    d <- add(a, add(b, c))""".stripMargin
     val check =
       """circuit Unit :
-         |  module Unit :
-         |    input a : SInt<10>
-         |    input b : SInt<10>
-         |    input c : SInt<4>
-         |    output d : SInt<15>
-         |    d <- shl(add(shl(a, 1), add(shl(b, 3), c)), 2)""".stripMargin
-    executeTest(input, check.split("\n") map normalized, passes)
+        |  module Unit :
+        |    input a : SInt<10>
+        |    input b : SInt<10>
+        |    input c : SInt<4>
+        |    output d : SInt<15>
+        |    d <- shl(add(shl(a, 1), add(shl(b, 3), c)), 2)""".stripMargin
+    executeTest(input, check.split("\n").map(normalized), passes)
   }
 
   "Fixed types" should "remove binary point shift correctly" in {
@@ -91,7 +95,8 @@ class RemoveFixedTypeSpec extends FirrtlFlatSpec {
       CheckFlows,
       new InferWidths,
       CheckWidths,
-      ConvertFixedToSInt)
+      ConvertFixedToSInt
+    )
     val input =
       """circuit Unit :
         |  module Unit :
@@ -104,7 +109,7 @@ class RemoveFixedTypeSpec extends FirrtlFlatSpec {
         |    input a : SInt<10>
         |    output d : SInt<12>
         |    d <= shl(a, 2)""".stripMargin
-    executeTest(input, check.split("\n") map normalized, passes)
+    executeTest(input, check.split("\n").map(normalized), passes)
   }
 
   "Fixed types" should "remove binary point shift correctly in reverse" in {
@@ -118,7 +123,8 @@ class RemoveFixedTypeSpec extends FirrtlFlatSpec {
       CheckFlows,
       new InferWidths,
       CheckWidths,
-      ConvertFixedToSInt)
+      ConvertFixedToSInt
+    )
     val input =
       """circuit Unit :
         |  module Unit :
@@ -131,7 +137,7 @@ class RemoveFixedTypeSpec extends FirrtlFlatSpec {
         |    input a : SInt<10>
         |    output d : SInt<9>
         |    d <= shr(a, 1)""".stripMargin
-    executeTest(input, check.split("\n") map normalized, passes)
+    executeTest(input, check.split("\n").map(normalized), passes)
   }
 
   "Fixed types" should "remove an absolutely set binary point correctly" in {
@@ -145,7 +151,8 @@ class RemoveFixedTypeSpec extends FirrtlFlatSpec {
       CheckFlows,
       new InferWidths,
       CheckWidths,
-      ConvertFixedToSInt)
+      ConvertFixedToSInt
+    )
     val input =
       """circuit Unit :
         |  module Unit :
@@ -158,7 +165,7 @@ class RemoveFixedTypeSpec extends FirrtlFlatSpec {
         |    input a : SInt<10>
         |    output d : SInt<11>
         |    d <= shl(a, 1)""".stripMargin
-    executeTest(input, check.split("\n") map normalized, passes)
+    executeTest(input, check.split("\n").map(normalized), passes)
   }
 
   "Fixed point numbers" should "allow binary point to be set to zero at creation" in {
@@ -197,7 +204,8 @@ class RemoveFixedTypeSpec extends FirrtlFlatSpec {
       CheckFlows,
       new InferWidths,
       CheckWidths,
-      ConvertFixedToSInt)
+      ConvertFixedToSInt
+    )
     val input =
       """
         |circuit Unit :
@@ -210,6 +218,6 @@ class RemoveFixedTypeSpec extends FirrtlFlatSpec {
         |  module Unit :
         |    node x = asSInt(asSInt(UInt<2>("h3")))
       """.stripMargin
-    executeTest(input, check.split("\n") map normalized, passes)
+    executeTest(input, check.split("\n").map(normalized), passes)
   }
 }