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AgeCommit message (Expand)Author
2018-03-21GroupModule Transform (#766)Adam Izraelevitz
2018-03-21Add SyntaxErrorsException as a type of ParserException (#770)Jack Koenig
2018-03-19Adding the firrtl proto. (#746)Kevin Townsend
2018-03-19Pass up annotations in return value from Driver.execute (#760)Chick Markley
2018-03-19Masks for zero-width fields of mems should be width zero. (#763)grebe
2018-03-02Reduce Statement nesting in Wiring Pass (#751)Jack Koenig
2018-03-02Fix annotation deserialization of component subfields (#750)Jack Koenig
2018-03-01[name change] Use LsbLargerThanMsbException (#740)Schuyler Eldridge
2018-02-27Refactor Annotations (#721)Jack Koenig
2018-02-27Add log-level debug message for modules that get deduped (#748)Jack Koenig
2018-02-26Rename loadAnnotations -> getAnnotations (#747)Jack Koenig
2018-02-23Add graph summation "+" to DiGraph (#744)Schuyler Eldridge
2018-02-22Add tests for #702. Adds Utility functions. Allows clock muxing in FIRRTL, bu...Adam Izraelevitz
2018-02-21Change primop arg type (#587)Adam Izraelevitz
2018-02-16Replacematcherror - catch exceptions and convert to internal error. (#424)Jim Lawson
2018-02-08CheckHighForm should check that Bits MSB >= LSB (#738)Schuyler Eldridge
2018-02-07Fix EulerTour for circuits with one module (#736)Schuyler Eldridge
2018-02-05Added comments to ExpandWhens (#716)Adam Izraelevitz
2018-01-30Make Constant Propagation respect dontTouch on registersJack Koenig
2018-01-30Fix bug incorrectly propagating constants on submodule inputsJack Koenig
2018-01-15WiringTransform Refactor (#648)Schuyler Eldridge
2018-01-05Fix FirrtlExecutionOptions backward incompatible change (#704). (#720)Jim Lawson
2018-01-05Remove erroneous undef of RANDOMIZE in emitted VerilogJack Koenig
2017-12-29Add support for multiple annotation filesJack
2017-12-29Actually emit annotations as YAML instead of default toStringJack
2017-12-29Remove option --force-append-anno-file, make defaultJack Koenig
2017-12-29Add Driver.dramaticWarningJack
2017-12-29Add logger printing for declarations removed by DCEJack Koenig
2017-12-29Add NodeCount analysis for helping with performance debuggingJack Koenig
2017-12-27Removed top preamble (#640)Adam Izraelevitz
2017-12-26Adjust isVCSAvailable commentedwardcwang
2017-12-22API change: out-of-bounds vec accesses now invalid, not first element (#685)Adam Izraelevitz
2017-12-20Verify shl/shr amount is > 0 (#710)Jim Lawson
2017-12-20Fix bug in ConstProp where module dependency edges were dropped (#696)Jack Koenig
2017-12-20Make submodule inputs void in ExpandWhens (#706)Jack Koenig
2017-12-20Add "checker" to the set of Verilog keywords - fixes 455. (#711)Jim Lawson
2017-12-19support -X sverilog to output xxxx.sv file (#638)Wei Song (宋威)
2017-12-19Make toNamed invert serialize (#709)Schuyler Eldridge
2017-12-15getBuildDir now builds full pathAdam Izraelevitz
2017-12-12Add RemoveWires transformJack Koenig
2017-12-12Improve MultiInfo emission, add apply that squashes NoInfoJack Koenig
2017-12-12Make object ConstantPropagation utilsJack Koenig
2017-11-29Add alternative graph IR (#671)Wenyu Tang
2017-11-28Have DedupModules report renamingJack
2017-11-28Refactor RenameMap to rename Components if their Module is renamedJack
2017-11-16Move digraph exceptions out of digraph class (#688)Albert Magyar
2017-11-10Make digraph methods deterministic (#653)Albert Magyar
2017-11-08Emit source locators as comments in emitted VerilogJack Koenig
2017-10-31Fix bug emitting and reparsing ExtModule String parameters (#675)Jack Koenig
2017-09-30Make ReplaceAccesses optimize multi-dimensional accesses (#665)Albert Magyar
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