Removed top preamble (#640)

2 files changed, 15 insertions, 32 deletions

diff --git a/src/main/scala/firrtl/Emitter.scala b/src/main/scala/firrtl/Emitter.scala
index edeb938d..094815ff 100644
--- a/src/main/scala/firrtl/Emitter.scala
+++ b/src/main/scala/firrtl/Emitter.scala
@@ -363,9 +363,7 @@ class VerilogEmitter extends SeqTransform with Emitter {
         case sx: Connect =>
           netlist(sx.loc) = sx.expr
           sx
-        case sx: IsInvalid =>
-          netlist(sx.expr) = wref(namespace.newTemp, sx.expr.tpe)
-          sx
+        case sx: IsInvalid => error("Should have removed these!")
         case sx: DefNode =>
           val e = WRef(sx.name, sx.value.tpe, NodeKind, MALE)
           netlist(e) = sx.value
@@ -564,15 +562,6 @@ class VerilogEmitter extends SeqTransform with Emitter {
           update_and_reset(e, sx.clock, sx.reset, sx.init)
           initialize(e)
           sx
-        case sx @ IsInvalid(info, expr) =>
-          val wref = netlist(expr) match { case e: WRef => e }
-          declare("reg", wref.name, sx.expr.tpe, info)
-          initialize(wref)
-          kind(expr) match {
-            case PortKind | WireKind | InstanceKind => assign(expr, netlist(expr), info)
-            case _ =>
-          }
-          sx
         case sx: DefNode =>
           declare("wire", sx.name, sx.value.tpe, sx.info)
           assign(WRef(sx.name, sx.value.tpe, NodeKind, MALE), sx.value, sx.info)
@@ -694,6 +683,18 @@ class VerilogEmitter extends SeqTransform with Emitter {
           emit(Seq("`endif"))
         }
         if (initials.nonEmpty) {
+          emit(Seq("`ifdef RANDOMIZE_GARBAGE_ASSIGN"))
+          emit(Seq("`define RANDOMIZE"))
+          emit(Seq("`endif"))
+          emit(Seq("`ifdef RANDOMIZE_INVALID_ASSIGN"))
+          emit(Seq("`define RANDOMIZE"))
+          emit(Seq("`endif"))
+          emit(Seq("`ifdef RANDOMIZE_REG_INIT"))
+          emit(Seq("`define RANDOMIZE"))
+          emit(Seq("`endif"))
+          emit(Seq("`ifdef RANDOMIZE_MEM_INIT"))
+          emit(Seq("`define RANDOMIZE"))
+          emit(Seq("`endif"))
           emit(Seq("`ifdef RANDOMIZE"))
           emit(Seq("  integer initvar;"))
           emit(Seq("  initial begin"))
@@ -706,6 +707,7 @@ class VerilogEmitter extends SeqTransform with Emitter {
           for (x <- initials) emit(Seq(tab, x))
           emit(Seq("  end"))
           emit(Seq("`endif // RANDOMIZE"))
+          emit(Seq("`undef RANDOMIZE"))
         }
 
         for (clk_stream <- at_clock if clk_stream._2.nonEmpty) {
@@ -724,22 +726,6 @@ class VerilogEmitter extends SeqTransform with Emitter {
    }
 
   /** Preamble for every emitted Verilog file */
-  def preamble: String =
-    """|`ifdef RANDOMIZE_GARBAGE_ASSIGN
-       |`define RANDOMIZE
-       |`endif
-       |`ifdef RANDOMIZE_INVALID_ASSIGN
-       |`define RANDOMIZE
-       |`endif
-       |`ifdef RANDOMIZE_REG_INIT
-       |`define RANDOMIZE
-       |`endif
-       |`ifdef RANDOMIZE_MEM_INIT
-       |`define RANDOMIZE
-       |`endif
-       |
-       |""".stripMargin
-
   def transforms = Seq(
     passes.VerilogModulusCleanup,
     passes.VerilogWrap,
@@ -747,8 +733,6 @@ class VerilogEmitter extends SeqTransform with Emitter {
     passes.VerilogPrep)
 
   def emit(state: CircuitState, writer: Writer): Unit = {
-    writer.write(preamble)
-
     val circuit = runTransforms(state).circuit
     val moduleMap = circuit.modules.map(m => m.name -> m).toMap
     circuit.modules.foreach {
@@ -771,7 +755,6 @@ class VerilogEmitter extends SeqTransform with Emitter {
         circuit.modules flatMap {
           case module: Module =>
             val writer = new java.io.StringWriter
-            writer.write(preamble)
             emit_verilog(module, moduleMap)(writer)
             Some(EmittedVerilogModuleAnnotation(EmittedVerilogModule(module.name, writer.toString)))
           case _: ExtModule => None
diff --git a/src/main/scala/firrtl/passes/RemoveValidIf.scala b/src/main/scala/firrtl/passes/RemoveValidIf.scala
index 06f0874a..68d16c30 100644
--- a/src/main/scala/firrtl/passes/RemoveValidIf.scala
+++ b/src/main/scala/firrtl/passes/RemoveValidIf.scala
@@ -30,7 +30,7 @@ object RemoveValidIf extends Pass {
   // Recursive. Replaces IsInvalid with connecting zero
   private def onStmt(s: Statement): Statement = s map onStmt map onExp match {
     case invalid @ IsInvalid(info, loc) => loc.tpe match {
-      case _: AnalogType => invalid // Unclear what we should do, can't remove or we emit invalid Firrtl
+      case _: AnalogType => EmptyStmt
       case tpe => Connect(info, loc, getGroundZero(tpe))
     }
     // Register connected to itself (since reset has been made explicit) is a register with no reset