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authorJack Koenig2017-10-31 16:09:26 -0700
committerGitHub2017-10-31 16:09:26 -0700
commitaaac74497b33bc62d3410e2269dad895d9bb71f1 (patch)
tree127a5057b80057098596735038e7e4f33a235cdd /src/main
parent3dd921f38f298c7c4aa338e14ac43bc77c652e8c (diff)
Fix bug emitting and reparsing ExtModule String parameters (#675)
Diffstat (limited to 'src/main')
-rw-r--r--src/main/scala/firrtl/ir/IR.scala2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/main/scala/firrtl/ir/IR.scala b/src/main/scala/firrtl/ir/IR.scala
index f2c39f8d..090ad8ec 100644
--- a/src/main/scala/firrtl/ir/IR.scala
+++ b/src/main/scala/firrtl/ir/IR.scala
@@ -481,7 +481,7 @@ case class DoubleParam(name: String, value: Double) extends Param {
}
/** String Parameter */
case class StringParam(name: String, value: StringLit) extends Param {
- override def serialize: String = super.serialize + value.serialize
+ override def serialize: String = super.serialize + value.escape
}
/** Raw String Parameter
* Useful for Verilog type parameters