diff options
| author | Schuyler Eldridge | 2018-02-07 19:52:50 -0500 |
|---|---|---|
| committer | Jack Koenig | 2018-02-07 16:52:50 -0800 |
| commit | d94157852d9414654331c7d9a2aaaf9bac17aede (patch) | |
| tree | 6e5c0b949a1e08c621b46d4d911a824503e7a4a3 /src/main | |
| parent | ec00c4b9befe8e9c477c574abfba5360a9443ad3 (diff) | |
Fix EulerTour for circuits with one module (#736)
A circuit with a single module would fail to properly compute BV RMQs due
to a divide by zero bug.
This changes the computation of the number of blocks an Euler Tour is
broken up into to be, at minimum, one.
This also changes one of the test cases ("wire with source and sink in the
same module") to exercise this.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
Diffstat (limited to 'src/main')
| -rw-r--r-- | src/main/scala/firrtl/graph/EulerTour.scala | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/main/scala/firrtl/graph/EulerTour.scala b/src/main/scala/firrtl/graph/EulerTour.scala index db25d8d0..29c97b20 100644 --- a/src/main/scala/firrtl/graph/EulerTour.scala +++ b/src/main/scala/firrtl/graph/EulerTour.scala @@ -59,7 +59,7 @@ class EulerTour[T](r: Map[T, Int], e: Seq[T], h: Seq[Int]) { // n: the length of the Euler Tour // m: the size of blocks the Euler Tour is split into private val n = h.size - private val m = math.ceil(lg(n) / 2).toInt + private val m = math.max(1, math.ceil(lg(n) / 2).toInt) /** Split up the tour into blocks of size m, padding the last block to * be a multiple of m. Compute the minimum of each block, a, and |