Fix EulerTour for circuits with one module (#736)

A circuit with a single module would fail to properly compute BV RMQs due
to a divide by zero bug.

This changes the computation of the number of blocks an Euler Tour is
broken up into to be, at minimum, one.

This also changes one of the test cases ("wire with source and sink in the
same module") to exercise this.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

2 files changed, 3 insertions, 11 deletions

diff --git a/src/main/scala/firrtl/graph/EulerTour.scala b/src/main/scala/firrtl/graph/EulerTour.scala
index db25d8d0..29c97b20 100644
--- a/src/main/scala/firrtl/graph/EulerTour.scala
+++ b/src/main/scala/firrtl/graph/EulerTour.scala
@@ -59,7 +59,7 @@ class EulerTour[T](r: Map[T, Int], e: Seq[T], h: Seq[Int]) {
   // n: the length of the Euler Tour
   // m: the size of blocks the Euler Tour is split into
   private val n = h.size
-  private val m = math.ceil(lg(n) / 2).toInt
+  private val m = math.max(1, math.ceil(lg(n) / 2).toInt)
 
   /** Split up the tour into blocks of size m, padding the last block to
     * be a multiple of m. Compute the minimum of each block, a, and
diff --git a/src/test/scala/firrtlTests/WiringTests.scala b/src/test/scala/firrtlTests/WiringTests.scala
index 5dd048a3..6da73157 100644
--- a/src/test/scala/firrtlTests/WiringTests.scala
+++ b/src/test/scala/firrtlTests/WiringTests.scala
@@ -395,17 +395,13 @@ class WiringTests extends FirrtlFlatSpec {
   }
 
   it should "wire with source and sink in the same module" in {
-    val sinks = Seq(ComponentName("s", ModuleName("A", CircuitName("Top"))))
-    val source = ComponentName("r", ModuleName("A", CircuitName("Top")))
+    val sinks = Seq(ComponentName("s", ModuleName("Top", CircuitName("Top"))))
+    val source = ComponentName("r", ModuleName("Top", CircuitName("Top")))
     val sas = WiringInfo(source, sinks, "pin")
     val input =
       """|circuit Top :
          |  module Top :
          |    input clock: Clock
-         |    inst a of A
-         |    a.clock <= clock
-         |  module A :
-         |    input clock: Clock
          |    wire s: UInt<5>
          |    reg r: UInt<5>, clock
          |""".stripMargin
@@ -413,10 +409,6 @@ class WiringTests extends FirrtlFlatSpec {
       """|circuit Top :
          |  module Top :
          |    input clock: Clock
-         |    inst a of A
-         |    a.clock <= clock
-         |  module A :
-         |    input clock: Clock
          |    wire pin: UInt<5>
          |    wire s: UInt<5>
          |    reg r: UInt<5>, clock