diff options
| author | Jack Koenig | 2017-12-20 13:18:33 -0800 |
|---|---|---|
| committer | GitHub | 2017-12-20 13:18:33 -0800 |
| commit | 4801d9cbc3cd957496daa00b099ead15f9f4e17d (patch) | |
| tree | ec92d7648107c8c79c4c3035aa9b684db461d30c /src/main | |
| parent | e3ea1000d4e4cce40fb7f583a55f4bd30115eb5d (diff) | |
Make submodule inputs void in ExpandWhens (#706)
Diffstat (limited to 'src/main')
| -rw-r--r-- | src/main/scala/firrtl/passes/ExpandWhens.scala | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/src/main/scala/firrtl/passes/ExpandWhens.scala b/src/main/scala/firrtl/passes/ExpandWhens.scala index 181fb642..6ff0debe 100644 --- a/src/main/scala/firrtl/passes/ExpandWhens.scala +++ b/src/main/scala/firrtl/passes/ExpandWhens.scala @@ -103,12 +103,16 @@ object ExpandWhens extends Pass { defaults: Defaults, p: Expression) (s: Statement): Statement = s match { + case stmt @ (_: DefNode | EmptyStmt) => stmt case w: DefWire => netlist ++= (getFemaleRefs(w.name, w.tpe, BIGENDER) map (ref => we(ref) -> WVoid)) w case w: DefMemory => netlist ++= (getFemaleRefs(w.name, MemPortUtils.memType(w), MALE) map (ref => we(ref) -> WVoid)) w + case w: WDefInstance => + netlist ++= (getFemaleRefs(w.name, w.tpe, MALE).map(ref => we(ref) -> WVoid)) + w case r: DefRegister => netlist ++= (getFemaleRefs(r.name, r.tpe, BIGENDER) map (ref => we(ref) -> ref)) r @@ -173,7 +177,8 @@ object ExpandWhens extends Pass { case sx: Stop => simlist += (if (weq(p, one)) sx else Stop(sx.info, sx.ret, sx.clk, AND(p, sx.en))) EmptyStmt - case sx => sx map expandWhens(netlist, defaults, p) + case block: Block => block map expandWhens(netlist, defaults, p) + case _ => throwInternalError } val netlist = new Netlist // Add ports to netlist |