| Age | Commit message (Collapse) | Author |
|---|
|
|
|
If 'import FIRRTLParser._' globally, 'FIRRTLParser.' is unnecessary.
|
|
Use getWidth function if it is suitable.
|
|
* Improve memoization for register const prop
|
|
|
|
* Convert the RemoveAccesses object into a class.
Prevent simultaneous access to common resources when tests are run in parallel.
* Respond to comments - use object factory to preserve existing API.
|
|
This gets rid of about 10% of the generated Verilog in the rocket-chip
default config.
|
|
should be parsable without excepting (#1060)
|
|
* Add serialization support for LoadMemoryFileType in LoadMemoryAnnotation
Add custom LoadMemoryFileTypeSerializer.
Add test to verify LoadMemoryAnnotation can be correctly serialized/deserialized.
* Simplify and focus LoadMemoryAnnotation serialization/deserialization.
Respond to comments on earlier implementations.
* Add type FileType definition for current chisel3 code.
|
|
* Copy MemConf.scala from ucb-bar/barstools#35 into memlib.
This provides a data structure wrapper around the existing memory conf format
which contains both reading and writing methods, making it easier to write code
that needs to read the format.
* Add MemConf tests and use a Map[MemPort, Int] for port lists instead of a Seq[MemPort] which is a bit less fragile.
|
|
* Don't create nodes to hold Muxes with >0 void cases
* Added test case demonstrating void error
* Memoize intermediate expression when checking for WVoid-ness
|
|
* Add --nodedup option to facilitate FIRRTL to verilog regression testing.
* Short-circuit the DedupModules transform if NoCircuitDedupAnnotation exists.
|
|
* Create a simple generic graphviz renderer for DiGraph
There are three basic kinds
- A simple default renderer
- A ranked renderer that places nodes in columns based on depth from sources
- A sub-graph render for graphs that contain a loop
- Renders just nodes that are part of first loop found
- Plus the neighbors of the loop
- Loop edges are shown in red.
* Create a simple generic graphviz renderer for DiGraph
- Moved the graph loop finder into DiGraph
- Fixed scala doc per Edward's comments
|
|
* Run CheckHighForm after all non-emitter transforms in firrtl tests
* Remove shlw from checks.scala
* Removed mistake in fix
* Fix FirrtlSpec fix
|
|
|
|
This fixes all Scaladoc warnings except for those trying to link to
Java.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
|
|
* refactor InferWidths to allow for extra contraints, add InferWidthsWithAnnos
* add test cases
* add ResolvedAnnotationPaths trait to InferWidthsWithAnnos
* remove println
* cleanup tests
* remove extraneous constraints
* use foreachStmt instead of mapStmt
* remove support for aggregates
* fold InferWidthsWithAnnos into InferWidths
* throw exception if ref not found, check for annos before AST walk
|
|
Instead, just forward the exception
|
|
|
|
|
|
* Correctly handle dots in loaded memory paths
* Added test for loadmem filename
|
|
Fixes #219
* Adds AsyncResetType (similar to ClockType)
* Registers with reset signal of type AsyncResetType are async reset
registers
* Registers with async reset can only be reset to literal values
* Add initialization logic for async reset registers
|
|
|
|
This uses the foldShiftRight method of the ConstantPropagation
Transform when legalizing Shr PrimOps. This has the effect of removing
literals with bit extracts from the MinimumVerilogCompiler.
This makes the formerly private foldShiftRight method of a public
method of the ConstantPropagation companion object.
Tests in the MimimumVerilogCompilerSpec are updated to check that Shr
is handled as intended.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
|
|
This adds the RemoveValidIf Pass to the MinimumLowFirrtlOptimization
Transform. A test case is included to verify that `is invalid` is
properly converted to a connection to zero.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
|
|
This adds "mverilog" to the "--compiler" command line option. This
will run the MinimumVerilogCompiler.
This additionally fixes the MinimumVerilogCompiler such that
DeadCodeElimination will not be run (it's not supposed to be). This is
done by adding a MinimumVerilogEmitter, subclassing VerilogVerilog,
that strips the DeadCodeElimination step from its parent.
Additionally, BlackBoxSourceHelper is removed from the
MinimumVerilogCompiler since this will be run by the VerilogEmitter
already.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
|
|
* Enhance constant propagation across registers
* Add more elaborate test case for register const prop
|
|
|
|
* Add memory WRef factory for completeness
* Refactor DefAnnotatedMemory construction for clarity
|
|
|
|
make more clear for ExecutionOptionsManager log level settings.
|
|
* Improve Shl codegen; eliminate Shlw WIR node
If we emit shl(x, k) as {x, k'h0} instead of (x << k), then there's
no need for Verilog-specific padding in the PadWidths pass. Avoiding
the redundant padding improves compiler/simulator performance and
renders Shlw unnecessary.
* [skip formal checks] Add test
|
|
|
|
|
|
Fixes #990
h/t @pentin-as and @abejgonzalez
|
|
|
|
This fixes issue #988
I tried one alternative to this fix: record the time to do a *no rename* run (`depth = 0`) and check that the time to do the *deep rename* (`depth = 500`) was a reasonable multiple of the *no rename* test. Unfortunately, the discrepancies were all over the map, sometime as much three orders of magnitude difference.
I decided the current fix was the simplest - don't enforce timing checks if we're doing coverage testing, although determining the latter is brittle.
|
|
Previously, components that did not affect the output would cause
exceptions because they were missing from the label2group Map. This
commit treats them as "reachable" by the ports so they are included in
the default "ungrouped" group.
|
|
This fixes an issue where expressions created by GroupComponents would
be improperly lowered because they were not marked as references to
instance ports.
|
|
|
|
* Seal Direction trait
* Add WRef factories for ports and instances
|
|
|
|
This adds a requirement that all Compilers must have at least one
Transform. Without this, there is no way to determine the inputForm or
outputForm of a given compiler as these are (rightly) defined in terms of
the head/last transform.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
|
|
This changes the NoneCompiler to be a unary sequence consisting of an
IdentityTransform. This fixes the inputForm and outputForm inherited
methods that implicitly mandate a non-empty transform sequence.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
|
|
This adds an identity transform that applies an identity function to some
CircuitState, i.e., it just returns the original CircuitState. This is
useful for transform generators that may, for edge cases, generate an
empty transform sequence. Other classes (e.g., Compiler) have explicit or
implicit requirements that a transform sequence is non-empty.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
|
|
* Give better error when mport references non-existent memory
* Closes #796
|
|
|
|
This fixes a bug where DiGraph summation (using the `+` operator) would
mutate the DiGraph. This occurred because the underlying edges set was not
being cloned. This is fixed to explicitly clone the underlying edges set.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
|
|
Iterating on a HashSet could cause identical modules (including
annotations) to not dedup
|
|
|
